Alphasil Incorporated

Energy Conversion Devices, Inc.

Other

Scott H Holmberg

Richard A Flasck

Benny Irwin

An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Method of manufacturing flat panel backplanes, display transistors

LCD screen illumination is provided by a neon tube formed to fit closely adjacent the screen. A tube formed to fit around the periphery of the screen shielded from the viewer's eyes can be utilized to front light the screen. A serpentine shaped tube can be placed adjacent the back of the screen to back light the screen. The tube can be formed to have a size coextensive with the screen configuration and can have a light diffuser between the tube and the screen to provide uniform illumination. The tube can provide any desired color, an adjustable high maximum surface brightness, high electrical efficiency and a narrow profile.

Method of illuminating flat panel displays to provide CRT appearing

Subdivided pixels are provided with interconnected and hence redundant row and column bus lines to reduce fatal defects. The respective redundant row and column lines also can be interconnected between subpixels to further reduce defects. One defective subpixel is generally an acceptable non-fatal defect, since the rest of the subpixels are still operative. The subpixels also can be formed with common row and column bus lines. The pixels or subpixels can be connected in a serial serpentine pattern to test all row or all column bus lines at once. After testing, the serial connections are broken.

Method of manufacturing flat panel backplanes including improved testing

Method of manufacturing flat panel backplanes, display transistors and

An improved method of manufacturing thin film transistors. A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor. To reduce shorts and capacitance between the gate and the source or the drain, a dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Method of manufacturing thin film transistors and transistors made

A programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and substantially non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 20 volts or less, a current of 25 milliamps or less, for 1000 microseconds or less. The cells in the conductive state have a resistance of 500 ohms or less. The cells have a maximum permittable processing temperature of 200.degree. centigrade or more and a storage temperature of 175.degree. centigrade or more. The cells can be formed from chalcogenide elements, such as germanium tellurium and selenium or combination thereof. The cells also can be formed from tetrahedral elements, such as silicon, germanium and carbon or combinations thereof. Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Programmable cell for use in programmable electronic arrays

An improved method of manufacturing thin film transistors. A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

An improved programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 10 volts or less, a current of 25 milliamps or less, for 100 microseconds or less. The cells in the conductive state have a resistance of 100 ohms or less. The cells have a maximum permittable processing temperature of 400.degree. centigrade or more and a storage temperature of 175.degree. centigrade or more. The cells are formed from doped silicon alloys including at least hydrogen and/or fluorine and contain from about 0.1 to 5 percent dopant. The cells can be plasma deposited from silane or silicon tetrafluoride and hydrogen with 20 to 150,000 ppm of dopant. Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Growing community of inventors

San Ramon, CA, United States of America

Scott H Holmberg