Hyundai Electronics America, Inc.

Image Quest Technologies, Inc.

Honeywell G.m.b.h.

Other

Coloray Display Corporation

Scott H Holmberg

Ronald L Huff

Rajesh Swaminathan

Shan Zhu

Quy Vu

An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the row lines and a second shorting bar is coupled to the column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

Active matrix ESD protection and testing scheme

Improved multilayer matrix line including inverted gate thin film matrix transistors to reduce defects in and enhance performance of matrix devices incorporating the transistors, including active matrix displays. The inverted gate line is formed in a multilayer metal structure deposited sequentially before patterning of a first bottom refractory layer, an aluminum layer and a second refractory layer for the gate structure. The aluminum layer is anodized adjacent the gate to prevent step coverage problems. A further improvement is provided when forming an active matrix display storage capacitor utilizing the multilayer gate structure.

Performance matrix, method of making an active matrix displays

Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor. A further improvement is provided when forming an active matrix display storage capacitor utilizing the dual insulator layer. A redundant column line can be formed utilizing a second overlying metal layer. A defect masking transistor also can be coupled from each pixel to the previous gate or row line.

TFT, method of making and matrix displays incorporating the TFT

An improved planar color filter structure to reduce defects in the display devices incorporating the color filter structures, including active matrix displays. A color filter substrate has a thicker polyamide black matrix formed thereon and a transparent polyamide layer formed over the black matrix. The transparent layer is exposed through the black matrix and developed to remove the unexposed portions over the black matrix. The resulting surface is substantially planar and facilitates the forming of the remaining layers to form a substantially planar color filter structure.

Color filter structure and method of making

Method of making an active matrix display incorporating an improved TFT

An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the odd row lines, a second shorting bar is coupled to the even row lines, a third shorting bar is coupled to the odd column lines and a fourth shorting bar is coupled to the even column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

Flat panel displays are provided with overlying interconnected and hence redundant bus lines to reduce fatal defects. The redundant, generally row lines are interconnected at least at two locations on a line and can be connected at each pixel to further reduce defects. The redundant row or gate line is formed by an overlying light shield line which preferably is of low resistivity and enhances the operation of the displays. The display can include subdivided subpixels and one defective subpixel is generally an acceptable non-fatal display defect, since the rest of the subpixels are still operative. The subpixels can be formed with common or redundant column bus lines.

Method of manufacturing flat panel backplanes including redundant gate

A matrix addressed flat panel display, is disclosed herein and includes a lower planar array of spaced apart, parallel, electrically conductive leads and a matrix array of field emission cathodes connected to and extending up from the lower planar array of electrically conductive leads. An upper matrix array of spaced-apart parallel electrically conductive leads is located above and spaced from the lower array of leads and from the cathodes, such that the upper leads extend normal to the lower leads, crossing the latter immediately above the cathodes, and such that those segments of the upper leads that actually cross over the lower leads are positioned in a plane closer to the lower leads than the rest of the upper leads. The upper and lower planar arrays of leads are electrically insulated from one another by means of a pair of separately formed layers of dielectric material disposed therebetween.

Matrix addressing arrangement for a flat panel display with field

Flat panel displays are provided including protection from electrostatic discharge (ESD) during manufacture and thereafter. At least one ESD guard ring is provided to protect the active elements of the display from the potential discharge between the row and column lines. An internal ESD guard ring is coupled to the row and column lines via shunt transistors. An external ESD guard ring is coupled to the row and column lines via a resistance. Both of the guard rings can be provided; however, the external guard ring is removed prior to completion of the display.

Growing community of inventors

Pleasanton, CA, United States of America

Scott H Holmberg