Motorola Corporation

Other

Molorola, Inc.

Scott G Nogle

Alan S Roth

Perry H Pelley

Stephen T Flannagan

Ruey J Yu

Shuang Li Ho

Walter C Seelbach

Hamed Ghassemi

Bruce E Engles

Robert P Dixon

John W Eagan

Ali R Farhang

A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

Pipelined dual port integrated circuit memory

An integrated circuit memory having a plurality of memory cells, output timing control means including frequency measurement means providing a frequency measurement count corresponding to a first frequency of the external clock signal and delay control means generating a delayed clock signal at the first frequency, wherein the delayed clock signal is delayed in time from the external clock signal in proportion to the first frequency, and data output control means outputting data from the plurality of memory cells responsive to the delayed clock signal. A method for adjusting output timing in a memory device including the steps of receiving an external clock signal, measuring a frequency of the external clock signal, generating a frequency count, determining an output delay proportional to the frequency, and generating an output clock at the external frequency and delayed from the external clock signal in proportion to the frequency.

Integrated circuit having output timing control circuit and method

A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells. A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) uses both a differential amplifier (360) included within a D-flip-flop circuit (114) and a reference voltage provided by a reference voltage circuit (365) to compare addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Comparison circuit utilizing a differential amplifier

Method and apparatus for amplifying a signal (50) to produce a latched digital signal (46). In one embodiment, an output stage circuit (24) of memory (10) includes a differential amplifier circuit (100), a level converter (102), a timing circuit (104), a clock-free latch (106), a high impedance control circuit (108), a high impedance control circuit (110), and an output driver (112). Output stage (24) requires one clock signal to function. Alternate embodiments may skew the disabling edge of the clock to improve the speed characteristics of output stage (24). In one embodiment, signal (50) is a differential pair of signals provided from a memory bit cell array (12).

Method and apparatus for amplifying a signal to produce a latched

A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

A circuit having a combined level conversion and logic function (37, 90, 101, 102, and 103) receives a differential CMOS level input signal, and an input signal having a relatively small logic swing, performs a logic operation, and provides a single-ended CMOS output signal. The circuit (37) includes a CMOS switching portion (71) and a small signal switching portion (75) connected to provide a CMOS output signal that is the result of a logical operation of the input signals. The circuits (37, 90, 101, 102, and 103), eliminate the need for a separate level converter, reducing at least a gate delay, and insuring faster generation of the output signal. Also, the use of the circuit (37) having a combined level conversion and logic function allows the cache TAG (20) to provide read data at the same time that a match signal is generated.

Circuit having combined level conversion and logic function

An output buffer circuit (20) has an output impedance that is adjustable. An external resistor (32) having a resistance that is a multiple of the desired output impedance is coupled to the output buffer circuit (20). A voltage across the resistor (32) is converted to a digital code using an analog-to-digital (A/D) converter (22). A digital code from the A/D converter (24) is used to adjust a resistance of a binary weighed transistor array (45) to match the resistance of the external resistor (32). A plurality of binary weighted output transistors (153, 154, 155) are selected in response to the digital code to adjust the output impedance to match the characteristic impedance of a load driven by the output buffer circuit (20). The output impedance is easily adjustable by changing the resistance of external resistor (32), allowing the output buffer circuit to drive various load impedances.

Buffer circuit having variable output impedance

A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

Address comparison in an inteagrated circuit memory having shared read

A combined global data line load and multiplexer comprises a decoder, a bias generator circuit, at least one output signal line pair, and a plurality of switching portions. The decoder provides a plurality of select signals in response to a portion of an address, each select signal provided at either a logic high voltage or at a logic low voltage. For example, a X4 memory internally organized X8 uses one extra address bit to select between two sets of four global data line pairs to provide as outputs. The bias generator circuit provides a bias signal at a voltage between the logic high and the logic low voltages. The output signal lines are each coupled through a respective resistor to a power supply voltage terminal. Each switching portion provides substantially a differential current between corresponding global data lines to corresponding output signal lines in response to the bias voltage exceeding a voltage of a corresponding select signal.

Memory with a combined global data line load and multiplexer

A BICMOS input stage includes a level shifting stage (35) and a level converter/buffer circuit (60). The input stage receives a single-ended GTL level input signal and a reference voltage, and in response, provides differential BICMOS level output signals. The input stage operates over a wide range of values for the reference voltage, does not require the generation of complex bias voltages, and provides well controlled output signals.

GTL compatible BICMOS input stage

A memory (30) includes input buffers (35, 38, 56), decoders (31, 32, 36), and a memory portion (34). The input buffers (35, 38, 56) include a delay circuit (82) which delays at least one transition of an input signal. The delay circuit (82) includes a compensation circuit (250) which compensates the delay circuit (82) for voltage, temperature, and processing variations. In one embodiment, the delay circuit (82) includes a CMOS inverter (102, 103) with an additional transistor (101) coupled between a source of an inverter transistor (102) and a corresponding power supply voltage. The compensation circuit (250) provides a bias voltage to bias a gate of the transistor (101) to determine the delay of the delay circuit (82). The compensation circuit (250) provides the bias voltage as that voltage which biases the transistor (101) to conduct a precision reference current.

Memory with compensation for voltage, temperature, and processing

A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.

BICMOS sense circuit for sensing data during a read cycle of a memory

A BICMOS bit line load for a memory includes first and second bipolar transistors having emitters respectively coupled to first and second bit lines of a differential bit line pair. Collectors of the first and second bipolar transistors receive a reference voltage. An equalization signal is applied to bases of the first and second bipolar transistors. The equalization signal is at a logic low voltage during a write cycle, and at a logic high voltage otherwise. In order to decrease the worst-case reverse bias, which causes bipolar transistors to degrade over time, a difference between the logic high voltage and the logic low voltage of the equalization signal is limited to a predetermined voltage.

BICMOS bit line load for a memory with improved reliability and a method

A BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) bit line load for a memory with improved speed write recovery and improved reliability. Comprises a first bipolar transistor, a resistor, and a second and third bipolar transistors respectively coupled to first and second bit lines of a differential bit line pair. The improvement in speed is accomplished through the use of the bipolar transistors which generally switch faster than corresponding MOS transistors. The first bipolar transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter coupled to the collectors of the second and third bipolar transistors. The resistor is coupled between the collector and emitter of the first bipolar transistor. The bit line load has improved reliability by preventing self-boosting at the bases of the second and third bipolar transistors by decreasing their collector voltages enough during switching to bias them into saturation.

BiCMOS bit line load for a memory with improved reliability

A low di/dt BiCMOS output buffer with improved speed for a device such as a memory includes an input portion, a level shifter, first and second logic portions, and an output stage. The input portion provides first and second signals respectively in response to positive and negative differences between true and complementary input signals. The level shifter decreases the first and second signals by a predetermined amount to provide third and fourth signals. When selected, the first and second logic portions provide a pullup signal and a pulldown signal respectively in response to the third and fourth signals to the output stage. The output stage provdes a data output signal at a logic high voltage in response to the pullup signal and at a logic low voltage in response to the pulldown signal.

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Austin, TX, United States of America

Scott G Nogle