Dsp Group Limited

Scott G Gibbons

Eric Unruh

A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

Co-prime division prescaler and frequency synthesizer

A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.

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San Jose, CA, United States of America

Scott G Gibbons