Marvell Asia Pte., Ltd.

Applied Micro Circuits Corporation

Qualcomm Incorporated

Marvell International Limited

Marvellworld Trade Ltd.

Scott Furey

Salil Suri

David Geddes

Liping Guo

Yingdong Li

Michael J Moretti

Thomas Wu

Noam Mizrahi

Dimitry Melts

Eitan Joshua

Chih-Lung Liu

Nedeljko Varnica

Joseph Jun Cao

Manish Shrivastava

A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.

Switch device for interfacing multiple hosts to a solid state drive

In a system with multiple host computers and one or more single-port non-volatile memory devices, a non-volatile memory switch receives memory transaction messages from different root complexes corresponding to the multiple host computers. Each of at least some of the memory transaction messages includes a host identifier that identifies a root complex from which the memory transaction was received. The non-volatile memory switch generates modified memory transaction messages at least by changing host identifiers within memory transaction messages to a common value indicative of a single root complex to present to the one or more single-port non-volatile memory devices the different root complexes as the single root complex. The non-volatile memory switch maintains associations of memory transaction messages with corresponding ones of the different root complexes, and sends the modified memory transaction messages to the one or more single-port non-volatile memory devices.

Non-volatile memory switch with host isolation

This disclosure describes a storage aggregator controller with metadata computation control. The storage aggregator controller communicates, via a host interface, over a computer network with one or more remote hosts, and also communicates, via a storage device interface, with a plurality of local storage devices, which are separate from the remote host(s) and which have respective non-volatile memories. The storage aggregator controller manages the local storage devices for storage or retrieval of media objects. The storage aggregator controller also governs a selective computation, at aggregator control circuitry or at a storage device controller of one or more of the storage devices, of metadata that defines content characteristics of the media objects that are retrieved from the plurality of storage devices or that are received from the one or more hosts over the computer network for storage in the plurality of storage devices.

Storage aggregator controller with metadata computation control

The present disclosure describes apparatuses and methods for automatically mapping virtual functions to storage media to enable single root input output virtualization. A storage media switch manages access to virtual functions that execute behind a storage media interface managed by the switch. The switch includes a host interface through which the switch receives host commands. The switch determines virtual function identifiers associated with the host commands and automatically selects the virtual functions of the storage media based on the virtual function identifiers. The switch executes the host commands over the storage media interface using the virtual functions, and after execution, responds via the host interface to each of the host commands. By automatically mapping virtual functions in this way, the switch automatically enables single root input output virtualization of storage media, including storage media that is without native support for input output virtualization.

Enabling virtual functions on storage media

The present disclosure describes apparatuses and methods for virtualizing isolation areas of solid-state storage media. In some aspects, a storage media accelerator determines, via a storage media interface, a geometry of solid-state storage media. The accelerator selects, based on the geometry, an area of the solid-state storage media as an isolated unit of storage. A physical address of the isolated unit of storage is then mapped to a virtual address. The accelerator exposes, via the virtual address, the isolated unit of storage through a host interface to enable host access of the isolated unit of storage. The accelerator may also remap the isolated unit of storage to other areas of the solid-state storage media without host interaction. By so doing, the accelerator may provide virtualized isolation and partitioning functionalities to a host, while efficiently handling lower-level storage media functions, such as wear leveling and load balancing, without host involvement.

Virtualizing isolation areas of solid-state storage media

A NVM switch has been designed that allows multiple hosts to simultaneously and independently access a single port NVM device. While this active-active multi-host usage configuration allows for a variety of uses of lower cost single port NVM device, an issue with one of the hosts can delay or block transactions between the other host and the NVM device. The NVM switch includes logic that isolates activity of the multiple hosts despite logic of the switch being shared across the hosts. When the switch detects an issue with one host ('error host'), the switch clears the in-flight commands of the error host and flushes data of the error host. Likewise, the NVM switch ensure proper communication of error reporting from attached NVM devices to the multiple hosts.

A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.

Managed switching between one or more hosts and solid state drives (SSDs) based on the NVMe protocol to provide host storage services

Embodiments described herein provide a method for accessing a host memory through non-volatile memory over fabric bridging with direct target access. A first memory access command encapsulated in a first network packet is received at a memory interface unit and from a remote direct memory access (RDMA) interface and via a network fabric. The first memory access command is compliant with a first non-volatile memory interface protocol and the first network packet is compliant with a second non-volatile memory interface protocol. The first network packet is unwrapped to obtain the first memory access command. The first memory access command is stored in a work queue using address bits of the work queue as a pre-set index of the first memory access command. The first memory access command is sent from the work queue based on the pre-set index to activate a first target storage device.

Methods and systems for accessing host memory through non-volatile memory over fabric bridging with direct target access

A hybrid storage device includes at least a first storage device operating under a first storage interface protocol, at least a second storage device operating under a second storage interface protocol, and a drive controller interface. The drive controller interface has a front-end for connecting to a host via a host interface protocol, a back-end for connecting to the first storage device via the first storage interface protocol, and to the second storage device via the second storage interface protocol, and a respective translation module for translating between the host interface protocol and a respective one of the first and second storage interface protocols. The hybrid storage device may be included in a hybrid storage system with a host processor. The host interface protocol may be the same as one of the first and second storage interface protocols, such as NVMe. The protocols may be implemented in hardware or software.

Hybrid storage device and system

The present disclosure describes apparatuses and techniques for tunneling transaction packets. In some aspects a packet is received from a peripheral device via a first data interface of a device. The packet includes an address for resource access and an identifier that identifies the peripheral device or a function thereof. Based on this identifier, it is determined whether the peripheral device is attempting to access an internal resource of the device or a resource of a host device connected to a second data interface of the device. If the peripheral device is attempting to access the resource of the host device, the packet is routed to the host device via the second data interface without modifying the address for resource access. By so doing, the peripheral device can exchange data with the host device without using address translation.

Tunneling transaction packets

Apparatus having corresponding methods and computer-readable media comprise: an interface to receive a first address in a first address space for one of a plurality of resources, wherein each resource is associated with a respective first aperture in the first address space, and a respective second aperture in a second address space; and a translation module to translate the first address to a second address in the second address space; wherein the translation module includes address translation logic to swap a first sequence of bits in the first address with a second sequence of the bits in the first address; wherein a number of the bits in the second sequence is determined according to a number of the resources; and wherein a number of the bits in the first sequence is determined according to a difference between a size of the first aperture and a size of the second aperture.

Address translation for SR-IOV virtual function apertures

A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Data frame processing

Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fiber Channel device to a storage processor on a packet-over-SONET network.

Growing community of inventors

Cupertino, CA, United States of America

Scott Furey