Micron Technology Incorporated

Other

Nan Ya Technology Corporation

Scott Eugene Smith

Kallol Mazumder

Tyler J Gomm

Christian N Mohr

Gary L Howe

Duc V Ho

Michael V Ho

John E Riley

J Thomas Pawlowski

Sujeet V Ayyapureddi

John Frederic Schreck

Brian W Huber

Vijayakrishna J Vankayala

Joshua E Alzheimer

Eric Booth

Yu-Feng Chen

Tony M Brewer

Debra M Bell

Matthew Alan Prather

Michael Amiel Shore

Daniel R Loughmiller

Brett Kenneth Dodds

Ross E Dermott

Miles S Wiscombe

Girish N Cherussery

Travis E Dirkes

Aaron Jannusch

Timothy Mowry Hollis

William B Dolan

Yoshinori Fujiwara

Anthony D Veches

Randall J Rooney

Jennifer E Taylor

Takayuki Miyamoto

William Chad Waldrop

Matthew B Leslie

Noriaki Mochida

Joo-Sang Lee

Stephen F Moxham

Thanh K Mai

Navya Sri Sreeram

Brian J Ladner

Scott Richard Cyr

Harish V Gadamsetty

Si Hong Kim

Mijo Kim

Manoj Vijay

Randy Brian Drake

Jack Riley

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses and methods for single-pass access of ECC information, metadata information or combinations thereof

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses and methods for configurable ECC modes

Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

Techniques for flexible self-refresh of memory arrays

Apparatuses and methods for repairing a memory are disclosed. In some examples, the memory may be a stacked memory that includes multiple die and at least one spare die. In some examples, a die may determine it is defective and provide signals causing the defective die to be disabled and a spare die to be enabled. In some examples, a component external to the memory, such as a memory controller, may determine a die is defective and provide signals causing the defective die to be disabled and a spare die to be enabled. In some examples, die may be enabled or disabled by fuses/antifuses.

Apparatuses and methods for die replacement in stacked memory

Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).

Metadata implementation for memory devices

An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.

Memory device clock swapping

Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

Adjusting refresh rate during self-refresh state

A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

Synchronous input buffer control using a ripple counter

An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

Low power clock injection during idle mode operations

Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages

Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.

Apparatuses and methods for bad row mode

Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

Apparatus with input signal quality feedback

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

Row clear features for memory devices and associated methods and systems

Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

Apparatuses and methods for decoding addresses for memory

Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

Memory with DQS pulse control circuitry, and associated systems, devices, and methods

Growing community of inventors

Plano, TX, United States of America

Scott Eugene Smith