Motorola Corporation

Other

Scott Edward Lloyd

Shay-Ping T Wang

Shao Wei Pan

ShaoWei Wei Pan

Nicholas M Labun

James Douglas Dworkin

Stephen L Smith

John Michael Buss

Sanjar Ghaem

David A Hayner

A method and system for a convolution operation in a digital signal processor (DSP) are provided. The convolution operation is performed in a logarithmic number system (LNS) domain. The DSP includes a plurality of processing elements that executes the convolution in a highly parallel fashion. The method can be implemented as a software program that directs a LNS based DSP to execute the convolution operation.

Method and system for performing a convolution operation

A method and system utilized by a multi-processor computer for storing exponent codes is provided. The multi-processor computer includes a plurality of processing elements. Each processing element executes a task having an instruction set. The processing elements are assigned a position in an execution sequence that defines the order in which the processing elements generate their respective outputs. Instruction sets are stored in a computer memory attached to the processing elements. The instruction sets are stored so that the processing elements produce outputs according to the execution schedule. The computer memory can be accessed using a two-dimensional addressing scheme where one dimension designates processing elements and the other designates instructions. Each instruction set includes one or more exponent codes that cause a processing element to raise an input value to a specified power.

Method and system for storing exponent codes in a multi-processor

In a method and system for storing a plurality of data blocks in a memory device, blocks of data elements are stored in a two-dimensional address space such that blocks overlap in the address space. The data elements may be digital words which represent exponents of a polynomial expansion. An overlapping data block is segmented into sub-blocks which are separated by null regions. Common data elements that are shared among the blocks are non-redundantly stored in the memory device.

Method and system of storing data blocks that have common data elements

A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.

Computer processor having a pipelined architecture and method of using

A computer processor that performs operations in a logarithmic number system (LNS) domain includes an input log converter (20), a feedback log converter (303), a first data pipeline (304), a second data pipeline (306), a plurality of processing elements (26a-f) coupled to respective stages of the data pipelines, an inverse-log converter (28), and a programmable accumulator (232) which produces output signals. An instruction, selected from a set of instructions, is decoded by a control unit (235) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters. The computer processor can be used as a co-processor (340) in a general purpose computer system.

Computer processor having a pipelined architecture which utilizes

A method and system for storing a plurality of data blocks in a memory device is disclosed. The method stores two blocks of data elements by assign different accessing methods to the two data blocks. Three example methods of accessing the data blocks are provided by the method. The first method allows data elements of a data block to be accessed by columns in the address space, the second allows data elements to be accessed by rows in the address space, and the third allows data elements to be accessed along diagonals in the address space. The data elements may be digital words which represent exponents of a polynomial expansion.

Method and system for storing data blocks in a memory device

A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Exponentiation circuit utilizing shift means and method of using same

An anti-lock braking system for a vehicle having a plurality of wheels, and a braking system that includes a brake for braking at least one of the plurality of wheels and a brake valve for controlling a braking pressure in the brake in response to a brake valve signal, includes a plurality of wheel speed sensors for generating a plurality of input signals. A polynomial processor, in communication with the plurality of wheel speed sensors, generates a control signal based on a nonlinear polynomial function of the input signal. A post-processor generates the Brake valve signal based on the control signal so as to provide cyclic control of the braking pressure in the brake.

Anti-lock braking system and method using a polynomial processor

A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from the processing elements, an accumulator which sums converted values from the inverse-logarithm converter, and a control unit for configuring the accumulator to perform various summing operations. The computer processor also includes a switch for providing processor outputs as feedback. An instruction, selected from a set of instructions, is decoded by the control unit to configure the computer processor to perform operations on a data stream.

Computer processor utilizing logarithmic conversion and method of use

Computer Processor utilizing logarithmic conversion and method of use

A method and system is described which allows execution overlap in a computer having a plurality of processing elements. The method and system provide an accumulation schedule based on the expected completion times of the processing elements. Outputs from the processing elements are accumulated according to the accumulation schedule. The accumulation schedule includes a plurality of accumulation flags which indicate when the outputs are to be accumulated.

Method and system for accumulating values in a computing device

A method for storing data in a memory device is provided. The method stores blocks of data elements in a two-dimensional address space such that the blocks overlap in the address space. The data elements may be digital words which represent exponents of a polynomial expansion.

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Hoffman Estates, IL, United States of America

Scott Edward Lloyd