Texas Instruments Corporation

Uatc, LLC

Scott E Smith

Duy-Loan T Le

Kallol Mazumder

Michael Duc Ho

Kenneth A Poteet

Michael C Stephens, Jr

Steven C Eplett

Matthew R Harrington

Charles J Pilch

Debra M Bell

Joshua E Alzheimer

Michael D Chaine

Masayoshi Nomura

Michael James Aitken

Brett Kenneth Dodds

Robert John Cyran

Scott Paul Gary

Vijaya B P Sarathy

Francis Hii

Edward Alan Anderson

Yutaka Komai

Aaron Jannusch

Anh Bui

Bangalore Kodandaram Srinath

Thuyanh Bui

M Kumar Rajith

Arthur R Piejko

Terry T Tsai

Michael V Ho

Duc Ho

Carl W Perrin

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

Semiconductor device with modified access and associated methods and systems

Systems and methods for facilitating communication with autonomous vehicles are provided. In one example embodiment, the autonomous vehicle telecommunications network system includes a first point-of-presence (POP) interface configured to obtain a first communication associated with a first autonomous vehicle and to route the first communication associated with the first autonomous vehicle. The autonomous vehicle telecommunications network system includes a first security system configured to authenticate the first autonomous vehicle. The first POP interface is separate from the first security system. The autonomous vehicle telecommunications network system includes a first data center system configured to receive the first communication associated with the first autonomous vehicle that is authenticated and to provide data to the first autonomous vehicle. The first POP interface is separate from the first data center system. The autonomous vehicle telecommunications network system can include a similarly configured second POP interface, second security system, and second data center system.

Telecommunications network for vehicles

Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to measure the power consumption of an embedded application at the task level as the application is executing on the target hardware. Methods and apparatus are provided to permit such measurements in both real-time and non-real-time.

System and method for power profiling of tasks

A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).

Burn-in mode detect circuit for semiconductor device

A circuit (,) that drives word lines and tests a word line (,) in a semiconductor device is disclosed. A charge circuit (,) couples a supply voltage (VPP) to a charge node (,) according to a potential at a boot node (,). The charge node (,) supplies a charge voltage for the word line (,). In a standard cycle, the boot node (,) is charged to a high voltage, and maintained at the high potential, to keep the word line (,) charged. In a test cycle, the boot node (,) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (,) and the word line (,). In the event the word line (,) suffers from current leakage, a drop in potential will be detected at the charge rode (,).

Circuit for driving conductive line and testing conductive line for current leakage

A circuit is designed with a detector circuit (,) coupled between a supply voltage terminal (,) and a reference voltage terminal (,). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (,) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (,) in response to the first and third control signals. A second circuit (,) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.

Timing circuit for high voltage testing

A bandgap reference circuit (,) with improved startup circuitry is disclosed. The bandgap reference circuit (,) includes a startup node (NBIAS) that is connected to the gates of n-channel MOS transistors (,) in first and second conduction legs of a current mirror. A series of inverters (,) turn on a transistor (,) that is connected between a precharge node (TO) and the startup node (NBIAS) in response to a signal (RID) indicating recent power-up of a power supply voltage (V,). A capacitor (,) is also provided, and which is discharged upon power-down. The capacitor (,) is connected to the gate of a p-channel transistor (,) that has its source/drain path connected between the precharge node (TO) and the startup node (NBIAS), and that is turned on upon power-up, even if the power-up signal (RID) is not generated, thus ensuring initiation of the bandgap reference circuit (,).

Startup circuit for bandgap reference circuit

A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Circuit and method for internal refresh counter

An integrated circuit includes a voltage supply internal to the integrated circuit and circuitry for sensing the voltage level of the internal voltage supply, the circuitry responsive to produce a flag signal, VPUEN, that is in a first logical state when the voltage level is below the desired level and in a second logical state when the voltage level is above the desired level. The integrated circuit also includes a buffer driver 406 having an input terminal and an output terminal, the input terminal being coupled to the circuitry for sensing the voltage level of the internal voltage supply. The operation of the circuit is such that the output terminal 400 of the buffer driver is in a high-impedance state when the flag signal is in the first logical state, and is responsive to data signals on the input terminal to produce corresponding output signals at the output terminal when the flag signal is in the second logical state.

Electrostatic discharge protection circuit and method

A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).

Data pipeline interrupt scheme for preventing data disturbances

An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply. In one embodiment, the large on-chip capacitor is a storage/filter capacitor (12) for a boosted high voltage supply (VPP), and the capacitive voltage reference is a memory cell reference voltage (VPLT) which is also connected to a reference plate of memory cell capacitors (28) of the memory cells (20) in the memory array.

Integrated circuit memory device having reduced stress across large

A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Testing and repair of wide I/O semiconductor memory devices designed for

A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

Write per bit with write mask information carried on the data path past

An MOS DRAM memory device includes an output buffer having an N-channel output transistor that must receive a boosted gate signal to produce a full Vdd output high logic level signal at the output terminal. The N-channel transistor connects between the Vdd supply voltage and the output terminal. The output buffer connects a Vdd supply voltage to the gate of the output transistor for a short period sufficient to raise the gate to the Vdd voltage level and then disconnects the Vdd supply. The buffer then connects a Vdd+ supply voltage to the gate to increase the gate voltage at least one transistor threshold value above the Vdd supply voltage. This provides the Vdd voltage at the output terminal.

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Sugar Land, TX, United States of America

Scott E Smith