Intel Corporation

Scott E Siers

Satish K Damaraju

Ruchira K Liyanage

Hon Shing Lau

Mohammad A Abdallah

Ak R Ahmed

Hans L Yeager

Subramaniam M Maiyuran

Sanjeev S Jahagirdar

Sanjay Dabral

Rajesh Bhikhubhai Patel

M Saif Islam

Belliappa Manavattira Kuttanna

Robert L Farrell

James Edward Phillips

Edward V Gamsaragan

Mehrdad Mohebbi

T W Griffith

Thu M Do

Andrew D Gerwitz

Omar Malik

Brian T Ormson

In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Power reducing logic and non-destructive latch circuits and applications

A device and method for reducing the power consumption of an electronic device using register file with bypass mechanism. The width of a pulse controlling the word write operation may be extended twice as long so that the extended portion substantially overlaps a following word read pulse. The extension of the pulse width of the read operation may enable lowering the Vcc Min value for the electronic device and thus may lower the power consumption of the device.

System and method for reducing power consumption in a device using register files

Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.

Memory cell write

A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.

Processor power consumption control and voltage drop via micro-architectural bandwidth throttling

Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Methods and apparatus for address generation in processors

A Dual Rail Time Borrowing Multiplexer (DTBM) generates a dual rail output from a single rail input with a one gate equivalent delay using a negative set up time. In one embodiment, a multiplexer includes a cross-coupled differential domino circuit coupled to a transistor array and to a data input and an enable input through a first and second circuit. The multiplexer outputs a dual rail output corresponding to a selected data input with a one gate equivalent delay using a negative set up time.

Dual rail time borrowing multiplexer

A domino circuit topology that includes a dynamic circuit, logic circuit, and static circuit. The domino circuit includes a dynamic circuit, logic circuit, and static circuit coupled through a central node. The dynamic circuit includes a pre-charge circuit and a keeper circuit for pre-charging the central node and keeping the central node at its current voltage level. The static circuit provides a static output for the domino circuit. The logic circuit provides logical functions for input signals. In addition, the domino circuit can include an isolation transistor coupled between the central node and the logic circuit.

Domino circuit topology

A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a&equals;(x,. . . x,) and a&equals;(y,. . . y,)where x,and y,have the same size for each i&equals;0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums x,&plus;y,, i&equals;0, 1, . . . , k, according to Boolean expressions, where for any sum x,&plus;y,where x,and y,each have size n,&plus;1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of x,&plus;y,do not exceed j&plus;1, where j is the largest integer not exceeding n,/2.

3X adder

A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.

Fast bi-directional tristateable line driver

A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial product selector groups, each partial product selector group includes a plurality of partial product selector circuits. Each partial product selector circuit receives a portion of a multiplicand as an input and outputs a partial product. The circuit also includes a plurality of Booth encoders. At least one of the Booth encoders is coupled to each partial product selector group. Each Booth encoder receives as an input a portion of a wide multiplier and outputs a Booth encoded value to at least a portion of a partial product selector group. The circuit further includes an override circuit coupled to one or more of the partial product selector circuits. The override circuit is operable to control one or more of the partial product selector circuits to output a zero to thereby avoid unwanted cross-products when performing multiple smaller multiplications using the same circuit.

Growing community of inventors

Elk Grove, CA, United States of America

Scott E Siers