Micron Technology Incorporated

Round Rock Research, LLC

Other

Scott E Schaefer

Aaron Preston Boehm

Todd D Farrell

Scott D Van De Graaff

Mark D Ingram

Todd Jackson Plum

Jeffery W Janzen

Brett L Williams

Matthew Alan Prather

Terry R Walther

Wen Qian Li

Mark R Thomann

Daniel R Loughmiller

Christopher S Johnson

Terry R Lee

Jongtae Kwak

Melissa I Uribe

Paul A LaBerge

Paul S Zagar

Steffen Buch

Jeffrey W Janzen

Methods, systems, and devices for memory die fault detection using a calibration pin are described. A memory device may perform a calibration procedure on a first resistor of each of a set of memory dies of a memory module using a pin coupled with the memory module. The memory device may couple the pin to a second resistor of a memory die of the set of memory dies based on the memory die identifying a fault condition for the memory die executing one or more of multiple commands from the host device. The memory device may receive, from the host device, a command to read a register of one or more memory dies of the set of memory dies and may output, to the host device, an indication of the memory die that identified the fault condition based on coupling the pin to the second resistor.

Memory die fault detection using a calibration pin

Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.

Techniques for indicating a write link error

Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

Techniques for detecting a state of a bus

Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

Individually addressing memory devices disconnected from a data bus

Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Error correction memory device with fast data access

Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

Indicating a status of a memory built-in self-test for multiple memory device ranks

Methods, systems, and devices for memory operations are described. A command may be received by a memory device and from a device. Both the device and the memory device may maintain counters of valid operations. A request for a value associated with a counter at the memory device may be received from the device. Based on receiving the request, a value of the counter may be transmitted to the device. The values of the counters may be compared to determine whether invalid data has been obtained by the device. Also, a pin associated with communicating error correction information may be coupled with a voltage source based on receiving a signal. The pin may remain coupled with the voltage source until a command is processed or an end of the signal. Whether the pin is coupled with the voltage source may indicate a validity of associated data.

Indicating valid memory access operations

Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test using a data mask inversion (DMI) bit. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first DMI bit of the memory device that is associated with indicating a status of the memory built-in self-test and a second DMI bit of the memory device that is not associated with indicating the status of the memory built-in self-test. The memory device may set the first DMI bit to a first value based on the one or more bits indicating that the memory built-in self-test is enabled. The memory device may perform the memory built-in self-test based on setting the first DMI bit to the first value.

Indicating a status of a memory built-in self-test using a data mask inversion bit

Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.

Methods and devices for error correction

Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the fault.

Differential strobe fault indication

Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.

Memory command verification

Methods, systems, and devices for evaluation of memory device health monitoring logic are described. A memory device may include health monitoring logic that is operable to be enabled in a configuration that corresponds to an output, such as an expected output, regardless of a degradation level of the memory device. Such a configuration may be enabled in a mode, such as a test mode, during which the memory device, or a host device coupled with the memory device, or some combination, may evaluate a difference between the output and an actual output of the health monitoring logic. The actual output being the same as the output may provide an indication that at least a portion of the health monitoring logic is functioning properly, and the actual output being different than the output may provide an indication that at least a portion of the health monitoring logic is not functioning properly.

Evaluation of memory device health monitoring logic

Methods, systems, and devices for inter-device communications for memory health monitoring are described. These communications relate to a host device that is associated with a memory device that monitors and reports health information (e.g., one or more parameters associated with a status of the memory device). The memory device may transmit the health information to the host device (e.g., a vehicle or a computer of the vehicle), which may perform one or more operations and transmit the health information to another entity of a system (e.g., ecosystem) including the host device. The host device may additionally or alternatively use the health information. In some cases, the other entity may receive the health information and transmit a signal back to the host device based on the health information. The other entity of the ecosystem may receive the health information and may make a determination based on the health information.

Inter-device communications for memory health monitoring

Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

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Boise, ID, United States of America

Scott E Schaefer