Cavium, Inc.

Marvell Asia Pte., Ltd.

Cavium Networks, Inc.

Marvell International Limited

Marvellworld Trade Ltd.

Scott E Meninger

Omer O Yildirim

David Lin

JingDong Deng

Lu Wang

Ethan Crain

Rohan Arora

Thomas Frederick Hummel

Thucydides Xanthopoulos

Jonathan K Brown

Mark Spaeth

Kyoungho Woo

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence

Serializer/Deserializer (SerDes) lanes with lane-by-lane datarate independence

A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.

Method and apparatus for multi-band voltage-controlled oscillator (VCO) band selection

In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.

Signal presence detection circuit and method

A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.

Clock and data recovery of sub-rate data

An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.

Multi-phase divider

A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.

Phase measurement and correction circuitry

In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear.

Voltage-controlled oscillator with improved tuning curve linearization

According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations.

Method and apparatus for reference voltage calibration in a single-ended receiver

An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the other semiconductor devices are devices not under test that produce, in the aggregate, a leakage current. There is an output node interconnected to the switching array for enabling the measurement of the test current at the output node. There is also a leakage current compensator connected to the output node and the switching array that is configured to divert the leakage current away from the output node.

Testing semiconductor devices

According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.

Method and apparatus for calibrating an input interface

According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

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Groton, MA, United States of America

Scott E Meninger