Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Sandisk Technologies Inc.

Acoustic Technologies, Inc.

Scott E Harrow

Gary D Hicok

Peter Chambers

Kenneth M Potts

Gregg D Lahti

Franklyn H Story

Rishi Nalubola

Judy Mae Fong

Robert W Ellis

David R Evoy

Laura Elisabeth Simmons

David Lee Dean

Edward Michael Petryk

Harold Downey

Donald Kesner

A test system, and a method of manufacture thereof, including: a thermal management head including a heat spreader; an electronic device in direct contact with the heat spreader; and an electrical current for transferring energy between the heat spreader and the electronic device.

Test system with localized heating and method of manufacture thereof

The amplitudes of a signal on the microphone input of a telephone and a signal on the line input of the telephone are compared with each other and with two thresholds. The comparisons are sampled and the samples control an up-down counter. The count in the counter is compared with two thresholds and the results of the comparisons are used to control at least two accumulators. A first accumulator counts consecutive comparisons having the same result and a second accumulator counts up or down in accordance with the comparisons. The counts in the first and second accumulators are logically analyzed to determine whether to receive or transmit. A plurality of samples defines a window, at the end of which the up-down counter is reset. The accumulators store data from a plurality of windows.

Transmit/receive arbitrator

This invention provides joystick interfaces and methods of providing position information of a joystick. According to one aspect, the invention provides a joystick interface for use with a joystick, the joystick interface being configured to selectively operate in one of a digital mode and an analog mode, the joystick interface including an interconnect adapted to couple with a host system; a timing circuit adapted to couple with a joystick having a lever and configured to output a timing signal having a timing characteristic which is dependent upon the position of the joystick lever; and logic circuitry coupled with the interconnect and the timing circuit and configured to initiate a timing operation within the timing circuit to generate the timing signal and output an indication signal responsive to the timing signal during operation in an analog mode of operation, the logic circuitry being further configured to generate and output a digital value to the interconnect responsive to the timing signal and during operation in a digital mode.

Joystick interfaces and methods of providing position information of a joystick

A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The present invention also generates a second sample page base address corresponding to a first part of a second address received from the DSP. The first and second generated sample page base addresses are then stored in respective first and second locations within a multiple entry sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a third address. Provided that the first part of the first address and the first part of the third address are the same, the present invention combines a second portion of the third address sent from the DSP with the first generated sample page base address stored in the multiple entry sample page base address cache. The first part of the second address is also compared with the first part of the third address. Provided that the first part of the second address and the first part of the third address are the same, the present invention combines the second portion of the third address sent from the DSP with the second generated sample page base address stored in the multiple entry sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Multiple entry wavetable address cache to reduce accesses over a PCI bus

A virtual contiguous system for combining multiple and arbitrarily-sized and aligned digital data packets from a PCI bus to a DSP circuit is disclosed. Information from the PCI bus is supplied directly to a plurality of FIFO RAM memory units. Each packet of digital data includes data packet descriptors identifying at least the start address for each data packet and the size of each data packet. The system utilizes this information to operate a read pointer and a write pointer to remove data from the FIFO RAM memory units on a sequential bit-by-bit basis and to supply said data packets to said RAM memory units by means of a write pointer operated by said control circuit. The information transfer is managed on the read side of the FIFO RAM memory units with minimal processing on the write side.

Virtual contiguous FIFO for combining multiple data packets into a

A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Wavetable address cache to reduce accesses over a PCI bus

An endian domain conversion circuit for converting data packets transmitted between two bus interfaces. The novel system advantageously eliminates any requirement for a large bit switch within the circuit's write data path. Instead, endian conversion intelligence is placed into the read data path. Double words (dwords) are individually received from an incoming data packet and bytes are parallel stored into the same byte location of several different first-in-first-out (FIFO) memories. In one example, the dwords are 32-bits each and the number FIFO memories used is four. An entire input data packet is received in this manner, incrementing the write address of the FIFO memories for each dword. Depending on the type of endian domain conversion required, if at all, endian conversion control circuitry of the present invention controls the manner in which the four exemplary FIFO memories are read (via a read pointer) and the manner which their data is supplied over the output bus to generate the output data. In one embodiment, a byte stream is generated over the output bus. Alternatively, dwords are sent over the output bus in proper endian domain format. Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet. The novel system is well suited to process arbitrarily sized data packets as well as data packets starting at arbitrary byte boundaries.

Virtual contiguous FIFO having the provision of packet-driven automatic

The present invention comprises a multiple functional block integrated circuit device for connecting to an external peripheral component interconnect (PCI) bus. The present invention includes an integrated circuit adapted to be coupled to an external PCI bus. The integrated circuit includes a plurality of functional blocks. Each of the plurality of functional blocks performs a function and comprises either a master functional block or a target functional block. A target bus adapted to transmit data signals is integral with the integrated circuit. The target bus is coupled to each of the plurality of functional blocks. A master bus adapted to transmit data signals is also integral with the integrated circuit. The master bus is coupled to each master functional block. A target bus interface integral with the integrated circuit is coupled to the target bus. The target bus interface is adapted to be coupled to the external PCI bus and to each of the plurality of functional blocks and interfaces each of the plurality of functional blocks to the external PCI bus. A master bus interface integral with the integrated circuit is coupled to the master bus. The master bus interface is adapted to be coupled to the external PCI bus and to each master functional block and interfaces each master functional block to the external PCI Bus.

Method and system for an extensible on silicon bus supporting multiple

The present invention relates to a system and a method for reducing access times for retrieving audio samples. The system uses a wave table cache. The wave table cache allows devices such as a Digital Signal Processor (DSP) to retrieve audio samples in a linear fashion from the wave table cache at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system. The DSP may then use the audio samples to generate signals to create sounds based on the audio samples.

System for reducing access times for retrieving audio samples and method

A method for storing and transferring wave table audio samples from system memory to a cache unit. The method creates a linked-list of pages in system memory for storing the audio sample. The linked-list is actually a pointer list indicating the locations in system memory where the audio samples are stored. A Digital Signal Processor (DSP) is able to translate the starting address of the pointer list to retrieve a requested audio sample from the system memory. The requested audio sample is then transferred to the cache unit where the DSP is able to retrieve audio samples in a linear fashion at a rate much faster than individually fetching the required portions of the audio sample from the main memory of the system.

Method for storing, transferring decompressing and reconstructing wave

A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.

Programming interface for a universal asynchronous receiver/transmitter

Method for storing and transferring wave table audio samples using a DSP

A digital power management system for an analog-to-digital converter operates to cause the sample rate of the analog-to-digital converter to function at an original desired frequency so long as changing input signals are present. Whenever activity at the input of the analog-to-digital converter ceases to change, the system automatically decreases the clock signal sampling rate to a slower clock frequency, or shuts down the application of clock signals. This conserves power until a change in the analog input is detected, whereupon the system automatically increases the sample clock frequency back to the original frequency.

Digital power management system

A joystick system is designed to provide a modified digital representation of the setting of a joystick potentiometer. The system operates to compensate for non-linearities and offsets in the joystick response, or may be used to enhance or vary the joystick response to a non-linear form. This is accomplished by supplying the output voltage of the joystick to an analog-to-digital converter, the output of which then is supplied to a lookup table. The lookup table output is provided to a counter. In one mode of operation, the counter counts down to zero at some multiple of a sample rate. When the counter reaches a zero count, the time interval representative of the joystick position is indicated; and the corrected or enhanced position is indicated by this output. In an alternative mode of operation, the counter is used as a data latch; and the corrected or enhanced joystick position is digitally read directly from the data latch where the data remains until the next sample cycle from the joystick position occurs.

System and method for enhancing joystick performance

A system is provided for digitizing the setting of a potentiometer of the type used in an analog joystick for computer games. The analog output of the potentiometer is applied to one of two inputs of a voltage comparator. When a readout of the joystick position is desired, a 'write' input is applied to a counter to permit it to commence counting at a predetermined frequency from an initial or zero count. The digital outputs of the counter are coupled to the inputs of a digital-to-analog converter, the output of which is coupled to the second input of the voltage comparator. When the count in the counter produces a voltage at the output of the digital-to-analog converter corresponding to the voltage setting of the potentiometer, the comparator provides an output signal. The time delay from the time the write pulse occurs until this signal is obtained is representative of the potentiometer setting. The system also provides a direct digital output from the counter by gating the counter outputs to a bus at the time the signal from the comparator is obtained. Thus, either a time interval representation of the potentiometer setting or a direct digital readout of the potentiometer setting may be obtained from the system.

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Scottsdale, AZ, United States of America

Scott E Harrow