Texas Instruments Corporation

National Semiconductor Corporation

Scott Douglas Kulchycki

Evgeny Fomin

Alfred Gomes

David Zakharian

Murali Srinivasa

Domenico Granozio

Matthew Christopher Kessler

Preeti Rajendran

A capacitive sensing system is adapted for noninvasive measurement of blood pulse (hear rate). A capacitive sensor is located near a skin pulse point exhibiting pulse displacement of skin tissue from vascular pulsation (for example, the temple area of the head), and includes a sensor electrode disposed over and spaced from the skin pulse point, such that the distance between sensor electrode and the skin pulse point cycles between a proximal and a distal displacement distance based on vascular pulsation. A capacitance-to-digital conversion (CDC) unit includes excitation circuitry providing sensor excitation to generate a sensor E-field between the sensor electrode and the skin pulse point based on sensor self-capacitance, and capacitance acquisition/conversion circuitry that acquires capacitance measurements for proximal and distal self-capacitance (for example, by multi-phase capacitive charge transfer using a switched capacitor arrangement), and converts these capacitance measurements into sensor data representative of vascular pulsation.

Blood pulse measurement based on capacitive sensing

A capacitive sensing system based on projected self-capacitance is suitable for use in printing systems/products to sense paper tray status. In example embodiments, a capacitive sensing system is adapted for sensing the condition/characteristics of paper in the paper tray, such as paper size, stack height and page count and paper dielectric. The capacitive sensing system can be configured with one or more shielded capacitive sensors incorporated into the paper tray, and oriented relative to the paper according to the paper condition/characteristic sensed.

Capacitive sensing for paper tray

A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width.

Analog-to-digital converter having output data with reduced bit-width and related system and method

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Mountain View, CA, United States of America

Scott Douglas Kulchycki