International Business Machines Corporation

Sony Computer Entertainment Inc.

Sony Interactive Entertainment Inc.

Scott Douglas Clark

Charles Ray Johns

Jeffrey Douglas Brown

Jeffrey Joseph Ruedinger

James Allan Kahle

David John Krolak

Dorothy Marie Thelen

Yuji Suzuki

Andrew Henry Wottreng

Daniel Frank Moertl

Bernard Charles Drerup

Gary Dale Carpenter

Russell Dean Hoover

Joseph Allen Kirscht

Thuong Quang Truong

Brian Thomas Vanderpool

Scott Michael Willenborg

Anil Pothireddy

Prasanna Srinivasan

Brian David Allison

Sudheendra Srivathsa

Ashish A More

Michael Kay Edwards

David Wayne Hill

Michael Norman Day

John David Irish

Richard Bealkowski

Kent Harold Haselhorst

Robert Allen Drehmel

Michael Joseph Corrigan

Michael Joseph Carnevale

Mark S Fredrickson

Paul William Rudrud

Larry Wayne Loen

Takeshi Yamazaki

Sudhir Dhawan

Randall Scott Jensen

Thomas K Pokrandt

Mark G Veldhuizen

Takeshi Sony Computer Entertainment Inc Yamazaki

Programmable data recorders are provided in a network semiconductor chip to monitor and record all or portions of data from various interfaces, including the input and output interfaces of network links interfacing the chip. A data recorder is provided for each network link. The data recorders store captured data in storage arrays. Data may be compressed and associated with time stamps to conserve space in the storage arrays. A data recorder manager in the chip may start and stop the data recorders at approximately the same time. The programmable mode of the data recorders determines which interfaces are monitored, the portion of data captured, and the format of the data in the storage arrays.

Integrated link-based data recorder for semiconductor chip

In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

Methods and apparatus for reducing command processing latency while maintaining coherence

Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

Low-cost cache coherency for accelerators

Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

Methods and apparatus for supporting multiple configurations in a multi-processor system

A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

Envelope packet architecture for broadband engine

Techniques for validating the integrity of a data communications link are provided. By executing error correction/detection calculations, such as CRC calculations, in a pipelined manner, logic may be distributed over multiple machine cycles. As a result, delay involved in the logic for each cycle may be reduced, allowing calculations in systems with higher clock frequencies.

Pipelined cyclic redundancy check for high bandwidth interfaces

Methods and apparatus provide for sending a data command from a first of a plurality of devices to a first address concentrator within a first of a plurality of processing systems; selecting one of the other processing systems, the selected processing system having data addressed by the data command stored therein; sending the data command to a first address concentrator of the selected processing system; and broadcasting the data command from the first address concentrator of the selected processing system to a second address concentrator in each of the processing systems.

Methods and apparatus for facilitating coherency management in distributed multi-processor system

In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.

Triple voting cell processors for single event upset protection

Disclosed is an apparatus and method for granting guaranteed bandwidth between one or more data transmission priority requesting sources and one or more resources upon request. Data sources that do not request an assigned bandwidth are served on a 'best efforts' basis. The system allows additional bandwidth to priority requesting sources when it is determined that the resource and/or the communication path to the resource is under-utilized. The system further allows the granted bandwidth to be shared by more than one source in a multiprocessor system.

Centralized bandwidth management method and apparatus

A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

Directory for multi-node coherent bus

A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and (2) generating an error injection trigger indicating when the pseudo-random error is to be inserted. Numerous other aspects are provided.

Methods and apparatus for error injection

Growing community of inventors

Rochester, MN, United States of America

Scott Douglas Clark