Intel Corporation

Scott Dion Rodgers

Gilbert A Neiger

Prashant Sethi

Andrew V Anderson

Steven M Bennett

Richard A Uhlig

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Anil Vasudevan

Ilan Pardo

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Barry E Huntley

Ohad Falik

Rajesh M Sankaran

Sebastian Schoenberg

Camron B Rust

Per H Hammarlund

Xiang Chris Zou

Hong Wang

Abraham Mendelson

Martin Guy Dixon

Gautham N Chinya

Bryant E Bigbee

Bret L Toll

Andrew F Glew

Baiju V Patel

Robert S Chappell

James Paul Held

Frank Binns

James S Coke

Peter J Ruscito

David B Jackson

Masood Tahir

Vedvyas Shanbhogue

John Thomas Shen

Shivnandan D Kaushik

Richard A Hankins

Asit K Mallick

Stalinselvaraj Jeyasingh

Avi Mendelson

Kamla P Huck

Anton Ivanov

Ves A Naydenov

David M Durham

Ravi L Sahita

Ittai Anati

H Peter Anvin

Xinmin Tian

Lawrence O Smith

Adriaan Van De Ven

Lawrence Smith, Iii

Stephen H Gunther

Darrell D Boggs

Anil Aggarwal

Chris J Newburn

Alain Kagi

Manohar Ruben Castelino

Mayank Bomb

Madhavan Parthasarathy

Taraneh Bahrami

Avi (Abraham) Mendelson

Uday R Savagaonkar

Carlos V Rozas

Edward Thomas Grochowski

Francis X Mckeen

Vincent R Scarlata

Koichi Yamada

Simon P Johnson

James B Crossland

Michael A Goldsmith

Ilya Alexandrovich

John P Shen

Wesley Hamilton Smith

Rebekah M Leslie-Hurd

Rajesh Sankaran Madukkarumukumana

Rinat Rappoport

Alex Berenzon

James D Beaney, Jr

Larry O Smith

Ed Grochowski

Alain Kägi

William Colin Wood

Anil Aggawal

Richard UhligQ

Mark Jay Charney

Jason W Brandt

Haitham H Akkary

Erik C Cota-Robles

William W Macy, Jr

Michael A Fetterman

Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

Protecting supervisor mode information

An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

Memory management apparatus and method for managing different page tables for different privilege levels

Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Virtualization exceptions

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Synchronizing a translation lookaside buffer with an extended paging table

Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Instructions and logic to provide advanced paging capabilities for secure enclave page caches

Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.

Systems, apparatuses, and methods for implementing temporary escalated privilege

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Virtualizing physical memory in a virtual machine system using a hierarchy of extended page tables to translate guest-physical addresses to host-physical addresses

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Growing community of inventors

Hillsboro, OR, United States of America

Scott Dion Rodgers