Intel Corporation

Dell Products Inc.

Other

Scott David Peterson

Sujoy Sen

Yadong Li

Phillip E Krueger

Anjaneya Reddy Chagam Reddy

David B Minturn

Yi Zou

Arun Raghunath

Mohan J Kumar

Murugasamy K Nachimuthu

Ziye Yang

Gang Cao

Bradley A Burres

Jose Niell

Cunming Liang

Changpeng Liu

Tony Hurson

Shaopeng He

Jason Philip Gross

Ranjit B Pandit

Haitao Kang

Noelan Olson

Charles Rego

Christopher August Shaffer

Christopher Mark Greiveldinger

Leslee L Peck

Gus Shaffer

Salma Mirza Johnson

Examples described herein relate to a network interface device comprising circuitry to receive an access request with a target logical block address (LBA) and based on a target media of the access request storing at least one object, translate the target LBA to an address and access content in the target media based on the address. In some examples, translate the target LBA to an address includes access a translation entry that maps the LBA to one or more of: a physical address or a virtual address. In some examples, translate the target LBA to an address comprises: request a software defined storage (SDS) stack to provide a translation of the LBA to one or more of: a physical address or a virtual address and store the translation into a mapping table for access by the circuitry. In some examples, at least one entry that maps the LBA to one or more of: a physical address or a virtual address is received before receipt of an access request.

Address translation at a target network interface device

Examples described herein relate to a network interface device that includes circuitry to perform operations, offloaded from a host, to identify at least one locator of at least one target storage associated with a storage access command based on operations selected from among multiple available operations, wherein the available operations comprise two or more: entry lookup by the network interface device, hash-based calculation on the network interface device, or control plane processing on the network interface device.

Initiator-side offload for scale-out storage

Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips. In one aspect the storage and server switches are Top of Rack (ToR) switches.

End-to-end data plane offloading for distributed storage using protocol hardware and PISA devices

Examples described herein relate to a network interface that includes an initiator device to determine a storage node associated with an access command based on an association between an address in the command and a storage node. The network interface can include a redirector to update the association based on messages from one or more remote storage nodes. The association can be based on a look-up table associating a namespace identifier with prefix string and object size. In some examples, the access command is compatible with NVMe over Fabrics. The initiator device can determine a remote direct memory access (RDMA) queue-pair (QP) lookup for use to perform the access command.

Offload of storage node scale-out management to a smart network interface controller

Technologies for providing efficient message polling include a compute device. The compute device includes circuitry to determine a memory location to monitor for a change indicative of a message from a device connected to a local bus of the compute device. The circuitry is also to determine whether data at the memory location satisfies reference data. Additionally, the circuitry is to process, in response to a determination that the data at the memory location satisfies the reference data, one or more messages in a message queue associated with the memory location.

Technologies for providing efficient message polling

Technologies for providing advanced management of power usage limits in a disaggregated architecture include a compute device. The compute device includes circuitry configured to execute operations associated with a workload in a disaggregated system. The circuitry is also configured to determine whether a present power usage of the compute device is within a predefined range of a power usage limit assigned to the compute device. Additionally, the circuitry is configured to send, to a device in the disaggregated system and in response to a determination that the present power usage of the present compute device is not within the predefined range of the power usage limit assigned to the present compute device, offer data indicative of an offer to reduce the power usage limit assigned to the present compute device to enable a second power utilization limit of another compute device in the disaggregated system to be increased.

Technologies for providing advanced management of power usage limits in a disaggregated architecture

Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.

Distributed storage location hinting for non-volatile memories

In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory communicatively coupled to the processor, the memory for storing a portion of a cache. The memory may be configured to receive a request to write data to the portion of the cache, write the data to the portion of the cache, and update a map corresponding to the cache and stored within the memory.

Systems and methods for tracking of cache sector status

A cache storage method includes providing a storage cache cluster, comprising a plurality of cache storage elements, for caching I/O operations from a plurality of virtual machines associated with a corresponding plurality of virtual hard disks mapped to a logical storage area network volume or LUN. Responsive to a cache flush signal, flush write back operations are performed to flush modified cache blocks to achieve or preserve coherency. The flush write back operations may include accessing current time data indicative of a current time, determining a current time window in accordance with the current time, determining a duration of the current time window, and identifying a current cache storage element corresponding to the current time window. For a duration of the current time window, only those write back blocks stored in the current cache storage element are flushed. In addition, the applicable write back blocks are flushed in accordance with logical block address information associated with each write back block.

I/O blender countermeasures

In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.

System and method for data redundancy within a cache

Systems and methods for cache load balancing by reclaimable block migration are described. In some embodiments, a computer system may include a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the computer system to: maintain a first list of reclaimable blocks that reside in a first caching device and a first advertised age for the oldest reclaimable block of the first list; maintain a second list of reclaimable blocks that reside in a second caching device and a second advertised age for the oldest reclaimable block of the second list; determine that the second advertised age is older than the first advertised age; and cause the oldest reclaimable block on the first list to be migrated from the first caching device to the second caching device.

Cache load balancing by reclaimable block migration

A method for information handling systems includes receiving a storage operation to be applied to a cache block in a location in a distributed storage system. The location is defined by a logical block address (LBA). The method further includes swapping a first portion of the LBA with a second portion of the LBA, resulting in a modified LBA, and performing the storage operation with the modified LBA. The first portion and the second portion are both x bits wide.

Striping cache blocks with logical block address scrambling

In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write data to a first portion of the cache, write the data to the first portion of the cache, update a first map corresponding to the first portion of the cache, receive a request to read data from the first portion of the cache, read from a storage communicatively linked to the computing system data according to the first map, and update a second map corresponding to the first portion of the cache. The cache manager may also be able to write data to the storage according to the first map.

System and method for updating data in a cache

In one embodiment, a computing system includes a cache having one or more memories, a cache journal operable to store data associated with one or more portions of the cache, and a configuration manager operable to access the cache and the cache journal. The configuration manager is operable to determine whether the cache journal includes data associated with a first portion of the cache, and to create, in the cache journal, data associated with the first portion of the cache if the cache journal does not yet comprise data associated with the first portion of the cache. The configuration manager is also operable to determine whether the first portion of the cache is valid for use, and to communicate with a memory manager associated with the first portion of the cache regarding whether the first portion of the cache is valid for use.

Growing community of inventors

Beaverton, OR, United States of America

Scott David Peterson