Ay Dee Kay LLC

Scott David Kee

Setu Mohta

Mohammad Radfar

Ichiro Aoki

Jeffrey Michael Zachan

Craig Petku

Aravind Loke

An integrated circuit that controls distributed temperature sensors in a semiconductor die is described. This integrated circuit may include: memory; a controller (such as a PTAT controller) coupled to the memory; temperature sensors distributed at measurement locations in the semiconductor die (such as remote locations from the controller), where a given temperature sensor includes building blocks (or components) that are common to the temperature sensors; and routing between the controller and the building blocks over an addressable bus, where signal lines for analog signals in the addressable bus are reused when communicating between the controller and different temperature sensors.

Multi-sensing PTAT for multiple-location temperature sensing

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Seamlessly integrated microcontroller chip

An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode. Furthermore, the digital processing circuit may correct an output signal from the ADC based at least in part on the characterized frequency-selective gain.

Frequency-selective compensation in ranging receivers utilizing chirped waveforms

An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.

Interface module with low-latency communication of electrical signals between power domains

An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.

Low latency, broadband power-domain offset-correction signal level circuit implementation

Dynamically configurable interconnect in a seamlessly integrated microcontroller chip

Security policy management in a seamlessly integrated microcontroller chip

Inter-die memory-bus transaction in a seamlessly integrated microcontroller chip

Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.

Time-interleaved dynamic-element matching analog-to-digital converter

Inter-die interrupt communication in a seamlessly integrated microcontroller chip

A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

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Aliso Viejo, CA, United States of America

Scott David Kee