Pragmatic Printing Limited

Pragmatic Semiconductor Limited

Scott Darren White

Brian Hardy Cobb

Richard John Price

Joao De Oliveira

Richard Price

Catherine Ramsdale

Neil Davies

Feras Alkhalil

Richard David Price

Ian Barton

Antony Sou

Anthony Sou

Ken Williamson

Kenneth David Williamson

Rob Mann

Gillian Ewers

Pascaline Boulanger

Thomas Stanley Van Den Heever

Nathaniel James Green

A signal measuring apparatus comprising: signal circuitry configured to receive an input signal to be measured; and memory circuitry coupled to the signal circuitry and configured to store information representing a magnitude of a voltage or a current of the input signal; wherein the memory circuitry comprises a first memory cell having a material which is arranged to switch from a first material state to a second material state in response to a first switching signal being applied thereto, wherein the first memory cell is tuned to a first value for the first switching signal so that a current or voltage with a magnitude at or above the first value will cause the material of the first memory cell to switch from the first material state to second material state; wherein the apparatus is configured to apply a measurement signal indicative of the input signal to the first memory cell for switching the material of the first memory cell from the first material state to the second material state in dependence on a magnitude of the voltage or current of the measurement signal.

Signal measuring apparatus

An interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly includes a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within the flexible base layer, and at least one first patterned contact layer, provided on any one of the first surface and the second surface of the flexible base layer and which is configured to operably interface with the at least one active electronic circuit component and the at least one 1C component.

Flexible interposer

The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (IC) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission parameters.

Multi-protocol RFID tag and system

A method, apparatus and system for secure one-way RFID tag identification is provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.

Secure RFID tag identification

A method, apparatus and system for secure one-way RFID tag identifications provided. The method comprising generating, at an RFID tag, an auxiliary identifier; generating, at an RFID tag, a secure representation based on the auxiliary identifier; transmitting, from the RFID tag and receiving at an RFID reader, one or more representations of the auxiliary identifier and the tag identifier including the secure representation; and verifying the identity of the RFID tag based on the received representations.

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

Electronic circuits

A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.

Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material

A method for use in the manufacture of an electronic circuit comprising at least one substantially planar electronic device is disclosed. The method comprises:

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Cambridge, United Kingdom

Scott Darren White