Azul Systems, Inc.

3dfx Interactive, Inc.

Other

Media Vision

Scott D Sellers

Jack H Choquette

Gil Tene

Gary Tarolli

James E Margeson, Iii

Michael A Wolf

Murali Sundaresan

Elias Atmeh

Kevin B Normoyle

Cliff N Click, Jr

Manuel Olivier Gautho

Edward C Frieberg

David Schmenk

Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.

Instruction based interrupt masking for managing interrupts in a computer environment

Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.

Cooperative preemption

A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster including a second plurality of processors associated with a second cluster cache, and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster. The first cluster includes a first unshared connection to the cluster communication network and the second cluster includes a second unshared connection to the cluster communication network.

Multiple cluster processor

Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

Array access

Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

Multi-level power monitoring, filtering and throttling at local blocks and globally

A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. The repair image is stored in non-volatile memory in the EEPROM die. At power-up, the repair image is copied from the EEPROM die to a volatile repair RAM in the embedded memory die. The redundant rows or columns are mapped to replace defective rows/columns using the repair image in the volatile repair RAM. Although the embedded-memory die has only volatile memory and no fuses, its embedded memory can be repaired using the repair map from the non-volatile EEPROM die. Since the EEPROM die is in the same dual-chip package as the embedded memory die, the repair map is always available.

Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information

A swimming pool drowning prevention safety system. The swimming pool drowning prevention safety system comprises: an article wearable by a person, a radio frequency transmitting device coupled to the article for transmitting a radio frequency signal, a microprocessor controlled radio frequency receiving station for receiving the radio frequency signal from the radio frequency transmitting device when the radio frequency transmitting device is within a user adjustable radio reception range of the radio frequency receiving station, and an alert signaling device coupled to the radio frequency receiving station for signaling when the person wearing the article has come within the user adjustable radio reception range of the radio frequency receiving station. The swimming pool drowning prevention safety system is further comprised of an adjustable gain control for varying the RF sensitivity of the radio frequency receiving station, and an RF sensitivity trigger circuit coupled to an audio messaging system for broadcasting at least one selected alert message. The swimming pool drowning prevention safety system further comprises telephone circuitry connection equipment for automatically connecting to a telephone system and transmitting the selected alert message. The swimming pool drowning prevention safety system further comprises a microprocessor that controls and integrates operation of the radio frequency receiving station.

Swimming pool drowning prevention system

A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local) and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)* F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local. Another feature of the invention is that multiple TCUs can be serially coupled to enable additional texture colors to be combined in a single execution path.

Texture compositing apparatus and method

A high quality texture filtering technique in a computer hardware system. The texture filtering quality of the present invention is comparable to trilinear filtering. However, the present invention reduces the number of memory accesses by fifty percent in comparison to trilinear filtering. To achieve this result, the present invention determines a pixel value based upon one or more texel values, e.g., four texel values, from only one of two mipmap levels. The mipmap level that is used is based upon the fractional portion of the LOD value and the position of the pixel. For a group of pixels having the same LOD value, the present invention performs a dithering operation that results in some pixel values being determined using texel values from the lower level mipmap and the remaining pixel values being determined using texel values from the higher level mipmap. The percentage of pixel values that are determined using texel values from the higher level mipmap is proportional to the fractional portion of the LOD value.

Level of detail texture filtering with dithering and mipmaps

A system and method for compressing and decompressing a texture image that: (1) compresses each texel to 8 bits, and when decompressed, each texel is of a quality comparable to a 256 color palettized image; (2) increases the efficiency of the decompression system and method by eliminating complex operations, e.g., multiplication; and (3) increases the efficiency of the system and method when switching between textures that use different palettes, when compared to conventional system and methods. The invention compresses a texture image, stores the compressed texture image, and quickly and efficiently decompresses the texture image when determining a value of a pixel. The texture image compression technique utilizes a palletized color space that more closely matches the colors in the texture image while allocating an unequal number of bits to the color channels. Each texel in the texture image is converted to an 8-bit value in the selected color space, and a decompression table is generated that represents the RGB values for the each texel stored in the selected color space. In order to map the texture image to the object, one or more texels that are associated with each pixel are decompressed. The present invention quickly and efficiently decompresses each texel using a hardware decompression unit. The decompression unit does not perform any multiplication operations.

System and method for narrow channel compression

A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local), and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)*F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local. Another feature of the invention is that multiple TCUs can be serially coupled to enable addition texture colors to be combined in a single execution path.

A system for generating blend values for three-dimensional graphic rendering includes a first register, a second register, third register, an index creation unit, a blend value generation unit and a blending unit. The first register receives and stores color pixel data, and the second register receives and stores a depth perspective component; and the third register receives and stores fog color data. The output of the second register is coupled to the index creation unit which uses the received depth perspective component to generate a two-part index. The two-part index is output by the index creation unit to produce a blend value. The first portion of the index is used to address a table in the blend generation unit, and the second portion of the index is used to produce an increment value added to output of the table resulting in the creation of a blend value. The blend value, the color pixel data and the fog color data are then blended by the blending unit and output by the system. The invention also includes a method for generating a blend value and producing a blended color output. The method includes the steps of: producing an index having a first portion and a second portion from a distance value; determining a base value using the first portion of the index, determining a delta between the base value and the next entry in the table using the first portion of the index, determining a blend increment using the delta and the second portion of the index; and producing a blend value by adding the base value to the blend increment; and blending the blend value with input pixel data.

System and method for efficiently determining a fog blend value in

The present invention provides a display subsystem which includes a frame buffer, a Digital to Analog Converter (DAC), a first color look up table and a second color look up table. The first color look up table is located in front of the frame buffer. The second color look up table is located between the frame buffer and the DAC. When the display subsystem receives a command that involves pixels from a Device Independent Bit Map (DIB) file, the translation table provided with the DIB is stored in the first color look up table. This translation table has a number of entries equal to the number of combinations available with the particular DIB format. For example, if the DIB has a one bit color format the first translation table has two entries one for each possible state of the color bits in the DIB. If the DIB uses a four bit color format the first table has sixteen entries, if the DIB uses an eight bit color format the table would have two hundred and fifty six entries, etc. The length of each entry in the first translation table conforms to the number of color bit planes in frame buffer. For example if the frame buffer accommodates twenty four bits for a true color display, each entry in the first translation table would have twenty four bits. The second color translation table is used to operate on the color bits which are read from the frame buffer. The second translation table translates the logical color information in the frame buffer into bits which generate the desired colors on the display.

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Tempe, AZ, United States of America

Scott D Sellers