Teradyne, Inc.

Scott D Schaber

Scott C Loftsgaarden

Howard Lin

An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

Managing memory in an electronic system

A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

Differential receiver architecture

A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Growing community of inventors

Roseville, MN, United States of America

Scott D Schaber