Sperry Corporation

Scott D Schaber

Gary D Burns

Donald W Mackenthun

An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Gray code counter with error detector in a memory system

An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described. The syndrome bits are applied to the adder circuits in predetermined groupings, and the carry signals from each of the adder circuits are applied to circuitry for detecting the occurrence of multiple bit errors. Selected ones of the decoded syndrome bits are utilized to determine the occurrence of single bit errors.

Read error occurrence detector for error checking and correcting system

A method of and an apparatus for differentiating between hard and soft failures of semiconductor memory cells for the purpose of error logging only hard failures. A spare bit position is appended to each addressable location within the semiconductor memory. The spare bit position is set, if the corresponding addressable location is observed to contain a single bit error during regeneration. The spare bit position is cleared, if the corresponding addressable location is observed not to contain a single bit error during regeneration. An error log entry is made for normal read access to an addressable location observed to contain a single bit error only if the spare bit is set indicating that a single bit error was present during regeneration of that addressable location.

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Saint Paul, MN, United States of America

Scott D Schaber