Intel Corporation

Other

Hewlett-packard Company

Scott D Hahn

David A Koufaty

Eliezer Weissmann

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

Ganapati Srinivasa

Paolo L Narvaez

Paul Brett

Abirami Prabhakaran

Andrew J Herdrich

Gaurav Khanna

Mishali Naik

Inder M Sodhi

Russell Jerome Fenger

Michael Mishaeli

David M Durham

Ravi L Sahita

Bret L Toll

Andrew D Henroid

Tong Li

Efraim Rotem

Glenn J Hinton

Jason W Brandt

Tsung-Yuan Charles Tai

Ren Wang

Ravishankar Iyer

Ronny Ronen

Boris Ginzburg

Stephen Anthony Fischer

Ashish V Choubal

Anil Aggarwal

Hisham Shafi

Raj S Yavatkar

Rinat Rappoport

Yuval Yosef

Priya Rajagopal

William Rash

Nagabhushan Chitlur

Oron Lenz

Sanjeev S Sahagirdar

Travis T Schluessler

Martin Guy Dixon

Christian Maciocco

Arvind A Kumar

James P Kardach

Alexander W Min

Guy M Therien

David B Papworth

Bryant E Bigbee

Hemal Vinodchandra Shah

Mona Vij

Lenitra M Durham

Aamer Jaleel

Arun Raghunath

Ali S Oztaskin

Avi Mendelson

Michael Mesnier

Gary Tsao

Carey W Smith

Ahmad A Samih

Carol Bell

Hisham Abu-Salah

John Keys

Ilya Osadchiy

Daniel P Baumberger

Arturo L Arizpe

Greg D Cummings

Bharath Muthiah

Weishuang Zhao

Kenzo Van Craeynest

Ellen M Deleganes

Michael D Shipley

Russel J Fenger

Richard Chuang

Avi Mendleson

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.

QoS based binary translation and application streaming

Embodiments of apparatuses and methods for adaptive data compression and associated contextual information are described. In various embodiments, an apparatus may include a context monitoring module to gather contextual information for transmission of data and a policy module to gather user preference on cost associated with transmission of data. The apparatus may further include an analysis module to determine whether to compress data prior to transmission, based at least in part on the contextual information and the user preference. Other embodiments may be described and/or claimed.

Apparatus and methods for adaptive data compression

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.

Instruction emulation processors, methods, and systems

An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

Apparatus and method for intelligently powering heterogeneous processor components

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Apparatus and method for heterogeneous processors mapping to virtual cores

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Hetergeneous processor apparatus and method

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

In one embodiment, the present invention includes a method for obtaining file information regarding a file to be downloaded from a remote location to a computing device, creating at least one empty file in a destination storage based on the file information and communicating block information regarding the empty file to a network interface, and receiving a data packet of the file in the network interface and directly sending a payload of the data packet from the network interface to the destination storage according to the block information, while a host processor of the computing device is in a low power state. Other embodiments are described and claimed.

Storing data using a direct data path architecture to reduce energy consumption and improve performance

A method, apparatus and system for selecting a highest prioritized task for executing a resource from one of a first and second expired scheduling arrays, where the first and second expired scheduling arrays may prioritize tasks for using the resource, and where tasks in the first expired scheduling array may be prioritized according to a proportionality mechanism and tasks in the second expired scheduling array may be prioritized according to an importance factor determined, for example, based on user input, and executing the task. Other embodiments are described and claimed.

Device, system, and method for multi-resource scheduling

A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory (RAM) responsive to the first and second processing cores. The processing system also features control logic to perform operations such as (a) automatically updating a resident set size (RSS) counter to correspond to the RSS for the thread on the first node in response to allocation of a page frame for a thread in the first node, and (b) using the RSS counter to predict migration overhead when determining whether the thread should be migrated from the first processing core to the second processing core. Other embodiments are described and claimed.

Thread migration control based on prediction of migration overhead

A paintbrush protection and revitalization system includes a case having a paintbrush support shelf with graduated bristle support projections and tapered tip support therein. The case has auto-convection ports, an air induction port and a brush insertion port. The auto-convection ports include at least one air inlet port and at least one water vapor exchange port for reducing drying time of a paintbrush contained within the case. A living hinge connects a cover to the case with the case, the cover and the living hinge being an integrally-molded unit, which is preferably made of plastic.

Brush glove

Growing community of inventors

Beaverton, OR, United States of America

Scott D Hahn