Intel Corporation

Scott Cline

Joshua B Fryman

Ankit More

Jason M Howard

Robert Pawlowski

Fabrizio Petrini

Wim Heirman

Vincent Cave

Shaden Smith

Samkit Jain

Michael Abbott

Sang Phill Park

Ivan Ganev

William Paul Griffin

Scott Hagan Schmittel

Paul Griffin

Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

Multithreaded processor core with hardware-assisted task scheduling

Disclosed embodiments relate to systems and methods for performing instructions to access a compressed graphic list. In one example, a processor includes fetch and decode circuitry to fetch and decode the single instruction to access the compressed graphic list, and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request, computing, via the first op-engine, a second data location associated with a second op-engine, computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request, and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications

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Beaverton, OR, United States of America

Scott Cline