Intel Corporation

Scott Chiu

Hiroshi Takatori

James Little

Vivek K De

Harish Krishnamurthy

Krishnan Ravichandran

Issy Kipnis

Mohamed Arafa

Xiaosen Liu

Claudia Patricia Barrera Gonzalez

Jing Han

Mohammed Sajid

Rajasekhara Madhusudan Narayana Bhatla

Keith Raynard Tinsley

Thomas J Barnes

Marc A Loyer

Jan Rapp

Rapp Jan

Jimmy Carlsson

David Westberg

Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

Reconfigurable load-reduced memory buffer

Embodiments include systems and methods for integration of RF components onto a single die with functional processing circuitry. For example, one integrated circuit may comprise multiple processors that can communicate there between by way of Radio Frequency (RF) transmission. The processors may also communicate with slave devices by way of radio frequency. Transmission and reception may be at frequencies in a band hitherto unused in computing devices and their peripherals.

Systems and methods for RF communication between processors

A device and method for canceling one or more self-jammer signals in a radio-frequency identification system.

Canceling self-jammer signals in an RFID system

Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio frequency identification system or the like is disclosed.

Canceling self-jammer and interfering signals in an RFID system

Provided are a method, system, and device directed to a receive path for a node in a communication system such as a Radio Frequency Identification (RFID) system. In one aspect, the receive path includes a filter operable in multiple modes and configurable to have different bandwidths in the various modes of operation. For example, in one mode, the filter samples a DC component while configured to have a relatively wide bandwidth. As another example, the filter may be operated in another mode to hold the sampled DC component while the filter is configured to have a zero or close to zero bandwidth. As yet another example, the filter may be operated in still another mode to filter received signals and cancel the sampled DC offset from the received signals while configured to have a relatively narrow bandwidth. Additional embodiments are described and claimed.

Filter scheme for receiver

Mechanisms for reducing amplitude-modulated noise in a wireless transceiver are generally described. In one example, an apparatus includes a radio-frequency identification (RFID) transceiver, a digital-analog converter (DAC) coupled with the transceiver, a reconstruction filter coupled with the digital-analog converter, and hold logic associated with the reconstruction filter to enable the reconstruction filter to hold its output voltage.

Reducing amplitude modulated noise for a wireless transceiver

A radio frequency device capable of differentiating self-jammer signals.

Detecting a self-jammer signal in an RFID system

A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.

Timing recovery with variable bandwidth phase locked loop and non-linear control paths

A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

Error correction method and apparatus for data transmission system

A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

Growing community of inventors

Folsom, CA, United States of America

Scott Chiu