Standard Microsystems Corporation

Other

Smsc Holdings Sarl

Delco Electronics Corporaiton

Cactus Semiconductor, Inc.

Scott Cameron McLeod

Madan G Rallabandi

Srinivas Kumar Pulijala

Lynn Russell Kern

Thomas R Anderson

Kenneth W Gay

Aniruddha Bashar

Robert St Pierre

William Castellano

Douglas L Smith

Steven Burstein

Leonid A Bekker

Chao-Ming Tsai

Joe A Marrero

Deandra McLeod

A chopper stabilized amplifier that utilizes a multi-frequency chopping signal to reduce chopping artifacts. By utilizing a multi-frequency chopping signal, the amplifier DC offset and flicker noise are translated to the higher chopping frequencies but are also smeared, or spread out in frequency and consequently lowered in amplitude. This lower amplitude signal allows for less stringent filtering requirements.

Pseudo-random chopper amplifier

A temperature sensor circuit and system providing accurate digital temperature readings using a local or remote temperature diode. In one set of embodiments a change in diode junction voltage (&#x394;V) proportional to the temperature of the diode is captured and provided to an analog to digital converter (ADC), which may perform required signal conditioning functions on &#x394;V, and provide a digital output corresponding to the temperature of the diode. DC components of errors in the measured temperature that may result from EMI noise modulating the junction voltage (V) may be minimized through the use of a front-end sample-and-hold circuit coupled between the diode and the ADC, in combination with a shunt capacitor coupled across the diode junction. The sample-and-hold-circuit may sample Vat a frequency that provides sufficient settling time for each Vsample, and provide corresponding stable &#x394;Vsamples to the ADC at the ADC operating frequency. The ADC may therefore be operated at its preferred sampling frequency rate without incurring reading errors while still averaging out AC components of additional errors induced by sources other than EMI.

Proportional settling time adjustment for diode voltage and temperature measurements dependent on forced level current

A voltage regulator may derive current from a bias circuitry having a constant-transconductance. The bias circuitry may generate the bias current using three NMOS devices. The temperature coefficient of the bias current may be within a specified, desired range. The bias current may be mirrored to low-power regulator circuitry to bias a diode-connected transistor in the low-power regulator circuitry to operate in the strong inversion region. A ratioed current based on the output load current may be injected into a bipolar junction transistor (BJT) device to cause the gate-source voltage (V) of the diode-connected device to track the Vof the output transistor of the voltage regulator, to ensure tighter load regulation. By operating the diode-connected transistor in strong inversion, by maintaining its (V) constant over temperature, and by cancelling the Vof the output transistor of the voltage regulator with the base-emitter voltage (V) of the BJT device, the regulated voltage output may become free of the effects of temperature and supply voltage.

Low power regulator

A control method for a brushless, three-phase DC motor. A voltage induced by rotation of a rotor may be sampled at a first expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values and the first sampled voltage value, may be calculated. The first sampled voltage value may be subtracted from the calculated average to produce a delta zero crossing error. A pulse-width modulation duty cycle may be adjusted based on the delta zero crossing error. The pulse-width modulation duty cycle may be used to control a rotational velocity of the rotor.

Brushless, three phase motor drive

A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

Circuit with high-density capacitors using bootstrapped non-metal layer

Fringe capacitor using bootstrapped non-metal layer

A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

High-density capacitor configured on a semiconductor

System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information.

Analog-to-digital converter in a motor control device

A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates/transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement.

Bi-directional high side current sense measurement

A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node.

Symmetrical electrical physical layer activity detector

Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

Electrical physical layer activity detector

A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device. A compensation capacitor and resistor may be coupled in series between the output of the error amplifier and the output of the voltage regulator to provide frequency compensation for the Miller-Effect.

Frequency compensation scheme for stabilizing the LDO using external NPN in HV domain

A fan driver circuit for powering a fan with a linear voltage may be designed using digital design techniques, resulting in a testable, accurate circuit on a smaller die size. The fan driver circuit may be configured to receive a digital control signal, which may be a sequence of numeric values, e.g. multiple-bit binary numbers, each indicative of a desired present rotational speed of the fan. The fan driver circuit may be implemented using a digital modulator, e.g. a delta-sigma modulator, with a simple low-pass filter, e.g. an RC-filter at the output, and may use oversampling based on a system clock, to shift in-band noise to out-of-band frequencies, and digital interpolation to filter out unwanted images from the upsampled digital control signal. The delta-sigma modulator may be constructed as a first-order delta-sigma modulator using an error-feedback structure to reduce die size.

Delta-sigma modulator for a fan driver

In one set of embodiments, a circuit may be implemented to deliver accurately ratioed currents to a remotely located semiconductor device that has a substantially non-linear input-output characteristic that varies with temperature and is subject to effects of electromagnetic interference (EMI). The circuit may be configured to use common mode rejection by establishing an identical impedance at each of the two terminals of the remotely located semiconductor device, in lieu of coupling shunting capacitor(s) across the terminals, in order to reject EMI signals while performing temperature measurements using the remotely located semiconductor device. This may facilitate maintaining fast sampling times when performing temperature measurements, while providing a more effective method for handling EMI induced currents that may lead to temperature measurement errors, thereby eliminating those errors.

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Oro Valley, AZ, United States of America

Scott Cameron McLeod