International Business Machines Corporation

Macronix International Co., Ltd.

Samsung Electronics Co., Ltd.

Scott C Lewis

Chung H Lam

Thomas M Maffitt

Jack Morrish

Masatoshi Ishii

Howard L Kalter

Kohji Hosokawa

SangBum Kim

Charles E Drake

John Edward Barth, Jr

William Paul Hovis

Daniel J Nickel

James A Yankosky

James Edward Rock

Hsiang-Lan Lung

John Atkinson Fifield

Jing Li

Hsin-Yi Ho

Pritish Narayanan

Chia-Jung Chen

Gordon A Kelley, Jr

David E Douse

Richard C Jordan

Theodore M Redman

Charles H Stapper

Donald Lawrence Wilder

David R Huffman

Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Writing multiple levels in a phase change memory

A system and method are shown for both forward and reverse read operations in a neuromorphic crossbar array that is part of an artificial neural network (ANN). During a forward read operation, a plurality of neuron activations are encoded into a pulse width drive array word line that gates a cell access transistor. A source-follower transistor is biased at a source follower voltage (VRDP) and a column voltage node (BLV) is held at read voltage (VREAD). During a reverse read operation, the cell access transistor operates as another source follower by: encoding a neuron error signal into the column voltage node (BLV), driving a gate line of the cell access transistor to the source follower voltage (VRDP), and holding an intermediate node between the cell access transistor of (a) and the source-follower transistor of (b) at the read voltage (VREAD).

Apparatus for deep learning operations on resistive crossbar array

Structures and methods for a multi-bit phase change memory are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Structures and methods for a multi-bit phase change memory, are provided herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models

A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

Phase change memory with an incrementally ramped write-reference voltage and an incrementally ramped read-reference voltage

Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period

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Essex Junction, VT, United States of America

Scott C Lewis