Intel Corporation

Scott Bruce Clendenning

Florian Gstrein

Rami Hourani

Szuya S Liao

Grant M Kloster

Matthew V Metz

Gilbert W Dewey

Abhishek A Sharma

Manish Chandhok

James M Blackwell

Ravi Pillarisetty

Donald S Gardner

Jeanette M Roberts

Roman Caudillo

Marko Radosavljevic

Han Wui Then

Niloy Mukherjee

Uygar E Avci

Ashish Verma Penumatcha

Carl H Naylor

Jack T Kavalieros

Robert S Chau

Van H Le

Kevin Lai Lin

Eungnak Han

Ian A Young

Benjamin Chu-Kung

Mauro J Kobrinsky

Patrick R Morrow

Rafael Rios

Patricio E Romero

Martin M Mitan

Sudipto Naskar

Sudarat Lee

Cheyun Lin

Cary L Pint

Robert L Bristol

Ehren Mannebach

Tristan A Tronic

John J Plombon

Urusa Alaan

Jasmeet S Chawla

Paul A Zimmerman

Chelsey Dorow

Kevin P O'brien

Kirby Maxey

Zhaohui Chen

Eric Charles Mattson

Cen Tan

Seung Hoon Sung

Aaron D Lilak

Paul B Fischer

Charles C Kuo

Eric Cabot Hannah

Sean T Ma

Hui Jae Yoo

Christopher J Jezewski

Nicole K Thomas

David J Michalak

Shriram Shivaraman

Ramanan Chebiam

Harsono S Simka

Nazila Haratipour

Sean W King

Marie Krysak

Tomm Aldridge

Lawrence D Wong

Michael L McSwiney

Jeffery D Bielefeld

Siddharth Chouksey

Aaron A Budrevich

Gurpreet Singh

Charles W Holzwarth

John L Gustafson

Daniel B Bergstrom

I-Cheng Tung

Jessica M Torres

Wei C Jin

Bum Ki Moon

Jitendra Kumar Jha

Mengcheng Lu

Thoe Michaelos

Tobias Brown-Heft

Kiran Chikkadi

Jiun-Ruey Chen

Lukas M Baumgartel

Diane Lancaster

Robert Edgeworth

Charles Mokhtarzadeh

Sunny Chugh

Ramanan V Chebiam

Kevin Obrien

Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.

Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

Integrated circuit interconnect structures with graphene cap

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

Stacked 2D CMOS with inter metal layers

Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.

Integrated circuit structures with graphene contacts

Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

Capacitor architectures in semiconductor devices

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

Halogen treatment for NMOS contact resistance improvement

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Self-aligned gate endcap (SAGE) architectures without fin end gap

Embodiments herein describe techniques for a semiconductor device including a substrate and a FinFET transistor on the substrate. The FinFET transistor includes a fin structure having a channel area, a source area, and a drain area. The FinFET transistor further includes a gate dielectric area between spacers above the channel area of the fin structure and below a top surface of the spacers; spacers above the fin structure and around the gate dielectric area; and a metal gate conformally covering and in direct contact with sidewalls of the spacers. The gate dielectric area has a curved surface. The metal gate is in direct contact with the curved surface of the gate dielectric area. Other embodiments may be described and/or claimed.

Gate stacks for FinFET transistors

A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

Vertically stacked memory elements with air gap

An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.

Local interconnect with air gap

Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Selective gate spacers for semiconductor devices

Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

Passivation layer for germanium substrate

Growing community of inventors

Portland, OR, United States of America

Scott Bruce Clendenning