Intel Corporation

Scott B Huck

Sunil R Shenoy

Konrad K Lai

Devadatta V Bodas

Justin J Song

Charles R Yount

Muralidhar Rajappa

Brian J Griffith

Jay S Heeb

Ramakrishna Huggahalli

Larry O Smith

Frank S Smith

Ilya Sharapov

Meenakshi Arunachalam

Lingdan (Linda) Zeng

A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.

Method to assess energy efficiency of HPC system operated with and without power constraints

A method and apparatus for performing bi-endian byte and short accesses in a single endian microprocessor. The present invention is used in a microprocessor or in a microprocessor in a computer system. The present invention provides a single endian microprocessor that promotes sub-word accesses to word accesses with a means for manipulating the two least significant bits of the access address to point to the correct sub-word data returned during an access to bi-endian external memory. The method for manipulating the address bits is also used to allow a single endian data cache to operate with the bi-endian external memory. The two LSBs of the address are manipulated such that the pointer values are A1# and A0# for word promoted byte accesses or cacheable accesses. For word promoted short accesses or cacheable accesses, the pointer values are A1# and A0. The present invention offers increased flexibility in interfacing a single-endian microprocessor with bi-endian systems. The present invention provides easy interfacing without undue or overly complex modifications to existing circuits.

Method and apparatus for performing bi-endian byte and short accesses in

An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.

Apparatus and method for an instruction cache locking scheme

A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected. The word positions within a row of the ROM are so ordered as to enable multiple words to be read out simultaneously regardless of what starting address is presented to the ROM. A second Y-mux (67) is provided between the cache RAM and the bus (19) for multiplexing the multiple words. The second Y-mux is controlled by at least one bit of the internally selected address. A multiplexer (74) is connected to the second Y-mux for shifting its input an appropriate amount according to bits of the starting address, such that the correct words are read out in the correct position.

High bandwith output hierarchical memory store including a cache, fetch

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Portland, OR, United States of America

Scott B Huck