Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Scott Arthur Jones

Thomas M Laffey

Alan Chris Berkema

Alonso Jose Carvajal Rojas

Thang Vinh Le

Rodolfo José Piedra Camacho

Maksim Nedorezov

Fred Joel Anast

Jairo Mendez

Eduardo Badilla Ramirez

Ted J Lopez

One aspect of the instant application can provide a system and method for packet mirroring. During operation, the system can determine, at a networking device, whether a packet meets a mirror trigger condition based on a first mirror criterion. In response to determining that the mirror trigger condition is met, the system can use a flexible hardware circuit to select, from a plurality of mirror passages, a particular mirror passage based on a second mirror criterion. The system can send the packet to the selected mirror passage, and the selected mirror passage can generate a replicate packet and process the replicate packet.

Expansion of packet mirroring functionality

A method and system for transmitting data between at least one receiver operatively connected to at least one transmitter, and more particularly to a method and a system for permissible transmission via at least one high-speed link having a plurality of virtual channels. The method includes the receiver sending a virtual channel credit packet for a particular virtual channel to the transmitter, the credit packet being indicative that the receiver is available to receive data and having a unique virtual channel number assigned to said particular virtual channel thereto. The transmitter responds to the virtual channel credit packet, which includes transmitting data to the receiver if data is available. The receiver receives the data transmitted from the transmitter.

Method and system for transmitting data between a receiver and a transmitter

The present invention provides a test and diagnosis system for testing an embedded processor. The test system includes an ASIC having an embedded microprocessor, a debug assist logic unit for monitoring the addresses and data from the embedded microprocessor, a debug kernel and an instruction overlay harness. When the debug assist logic block finds a predetermined set of match conditions, it interrupts the embedded microprocessor and transfers control from the code running on the microprocessor to the debug kernel. The debug kernel is coupled to the debug assist logic unit and responsive to user input, the debug kernel allows the user to trace processor transactions during code execution. A REMAP bit in the ASIC allows remapping of the microprocessor memory into a faster instruction overlay memory, allowing the code to be quickly modified during product debug.

Hardware-assisted firmware tracing method and apparatus

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Rocklin, CA, United States of America

Scott Arthur Jones