Cypress Semiconductor Corporation

Scott Anthony Jackson

Jeffery Scott Hunt

George M Ansel

A circuit and method for starting up a band-gap reference circuit. In one example, a startup circuit compares a Vbg voltage output of a band-gap reference circuit to a voltage (such as Vbe) across a transistor in order to selectively control whether to inject current into the band-gap reference circuit during startup.

Circuit and method for startup of a band-gap reference circuit

Systems and methods for stacked die memory depth expansion. In accordance with a first embodiment of the present invention, a circuit comprises a first memory input enabling depth expansion in a memory. The circuit further comprises a second memory input enabling address range selection in a memory and a plurality of address inputs accessing an expanded memory depth. The circuit also comprises one or more external chip enable inputs and a decoding logic coupled to the first memory input, second memory input, plurality of address inputs and the external chip enable input, wherein the decoding logic generates an internal chip enable signal and a stacked die select signal.

Stacked die memory depth expansion

A regulator circuit including output loading sense circuitry where the output loading sense circuitry comprises, in one example, a resistor in the feedback leg of the replica bias regulator, a switch in the feedback leg of the replica bias regulator for bypassing the resistor, and a comparator used to sense the output loading and selectively drive the switch.

Replica bias regulator with sense-switched load regulation control

A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.

Buffer circuit using low voltage transistors and level shifters

An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

Input buffer system using low voltage transistors

A decoupling circuit comprising a first capacitor, and a first current mirror coupled to the capacitor, wherein the first current mirror is configured to multiply the capacitance effect of the first capacitor is disclosed. The first current mirror may comprise a first transistor, and a second transistor coupled to the first transistor, wherein the second transistor is configured to amplify the current entering the first transistor. The first transistor and the second transistor may comprise n-channel MOSFET transistors. The decoupling circuit may further comprise a bias network coupled to the first current mirror, wherein the bias network is configured to bias the first current mirror. The bias network may comprise a p-channel MOSFET.

Growing community of inventors

Starkville, MS, United States of America

Scott Anthony Jackson