Cypress Semiconductor Corporation

Parade Technologies, Ltd.

Scott Allen Swindle

Steven Philip Larky

Paul Kelleher

Aaron Hogan

Hans Van Antwerpen

John Boynton

Warren S Snyder

Lane Thomas Hauck

Syed B Raza

Hamid Khodabandehlou

Steve Kolokowsky

Erik Anderson

Mark D McCoy

Paul D Berndt

Drew Marshall Harrington

Michael L Lewis

Steve Kolokowsly

Mike Lewis

An embodiment of a method for detecting noise for a capacitance sensing panel may comprise generating an input signal based on a noise signal, performing a series of measurements for measuring capacitances from a capacitive sensor sensitive to the noise signal, and controlling timing for at least one of the subconversions based on the input signal.

Noise detection for a capacitance sensing panel

Method and apparatus for automating noise reduction tuning in real time

A system and method for synchronization of touch-panel devices is described. In one embodiment, the system includes a first controller device configured to control operations of a first portion of a touch-panel device such that the first controller device is further configured to generate a single master timing signal. The single master timing signal is configured to synchronize operation of the first controller device and a second controller device that is configured to control operations of a second portion of a touch-panel device.

System and method for synchronization of touch panel devices

A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.

Programmable system-on-chip hub

A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.

Devices and methods for sharing common target device with two different hosts according to common communication protocol

An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the first speed.

Apparatus and method to test high speed devices with a low speed tester

An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Method and apparatus implementing a FIFO with discrete blocks

A circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.

Real-time I/O processor used to implement bus interface protocols

A USB device for communicating data from the device to a USB host is provided. The USB device may have an interrupt or isochronous endpoint for communicating interrupts to the host and a bulk data endpoint for communicating bulk data to the host. The USB device may communicate a signal over the interrupt or isochronous endpoint to the host indicating that the device has bulk data to communicate to the host and may communicate bulk data over the bulk endpoint in response to bulk data requests from the host generated based on the signal over the interrupt or isochronous endpoint. The device may count a predetermined period of time when the device is generating a NAK signal in response to the bulk data request signals from the host because the device does not have any bulk data, and may communicate a signal over the bulk endpoint to the host, once the predetermined period of time has elapsed, indicating that the host halts the bulk data requests until another signal over the interrupt or isochronous endpoint is received.

Device and method for efficient bulk data retrieval using a universal serial bus

A device and method for interconnecting two universal serial buses (USBs) is provided in which the device controls the current supplied to the device from the USBs via a power manager. In particular, when one or both of the buses connected to the device enter a suspended state, the power manager reduces the current consumed by the device so that the device does not exceed a maximum suspend current. The device may also have a power manager controller which permits one or both device drivers connected to the USBs to control the power manager.

Device and method for interconnecting universal serial buses including

A USB-to-USB connecting device is provided for interconnecting two independent universal serial buses (USBs) and for synchronizing local device clocks to the data streams of both USBs. To interconnect the USBs, the device may include a separate local clock synchronization mechanism for each USB connected to the device. Each separate local clock synchronization may utilize the same reference clock. A method for interconnecting two USBs is also provided.

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Cardiff by the Sea, CA, United States of America

Scott Allen Swindle