Lsi Corporation

Lsi Logic Corporation

Scott Allen Peterson

Michael Norris Dillon

Gary Scott Delp

Ramnath Venkatraman

Subramanian Ramesh

Carl Anthony Monzel, Iii

David A Gardner

Robert C Armstrong

Donald Thomas McGrath

Kenneth G Richardson

Scott C Savage

Richard Karl Kirchner

Bret Alan Oeltjen

Christopher J Tremel

Khosro Khakzadi

Donald Ray Amundson

A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Basic cell architecture for structured ASICs

A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Basic cell architecture for structured application-specific integrated circuits

An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

Configurable I/Os for multi-chip modules

Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of macros are identified, and a common element is placed on the platform for an identical element of at least two macros. All other elements of the macros are placed at locations on the platform relative to the common element as to satisfy macro placement rules for each macro. Identical elements can be identified by identifying similar elements in a plurality of macros, and creating a common element generic to the similar elements. The user designs a metalization layer to select macros and configure common elements to the selected macros.

Process for designing base platforms for IC design to permit resource recovery and flexible macro placement, base platform for ICs, and process of creating ICs

An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file. The flow framework and methodology creates a sequence of flows to design the semiconductor product, and each flow, when properly executed, results in a set of deliverables that are input to the next flow. The flows include not only the evolution of the design from a high-level behavioral description to a physical implementation, but also the verification of the specified functions and of manufacturability. Delivered to the customer is a design kit having the tested and validated flow files, along with the flow manager that executes the flow files. Using the design kit, a designer of a semiconductor product can input her/his chip specification; output will be final testable and verifiable design views for a manufacturing facility of the semiconductor product.

Automation of the development, testing, and release of a flow framework and methodology to design integrated circuits

A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.

Method of using filler metal for implementing changes in an integrated circuit design

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Bloomington, MN, United States of America

Scott Allen Peterson