Cirrus Logic Inc.

Silicon Laboratories Inc.

Scott Allan Woodford

Daniel John Allen

John Christopher Tucker

John L Melanson

Eric J Swanson

Zhong You

Steven Green

Marc Laurent Tarabbia

Anand Ilango

Robin Matthew Tsang

Harish Raghavan

An integrated sense resistor within an integrated circuit (IC) may be surroundingly positioned near and coupled to a connection such as a pin or ball. The integrated sense resistor may be shaped such that more surface area of the integrated sense resistor is coupled to be positioned closer or in actual contact with the pin or ball than conventional straight layered integrated sense resistor solutions. The integrated sense resistor may be a non-straight shape that entirely surrounds or wraps around a connection to the pin or ball, such as a circular or oval shape, a box or rectangular shape, a triangular shape, or a polygonal shape. The integrated sense resistor may be a non-straight shape that partially surrounds a connection to the pin or ball, such as an open-circular or semi-circular shape, an open-sided box or rectangular shape, an open-sided triangular shape, an angular shape, or an open curved shape.

Sense resistor surroundingly positioned near or around and integrated with an output connection

A voltage reference circuit provides a precision voltage reference output without requiring a filter capacitor. The voltage reference output is generated by a digitally-controlled source, which has a value set by the output of a digital filter that filters the output of a comparison circuit that compares the voltage reference output to another reference. A selectable mode can be provided to provide a fast response during a startup/reset period and an optional hold or narrowband response after startup. The mode selection may also offer selection of an externally-supplied digital control value and/or a resistor divider type voltage reference as an alternative to the digitally-controlled source.

Low-noise voltage reference generator with digitally-filtered reference matching

A modulated gain audio control and zipper noise suppression techniques provide reduction in audible artifacts caused by discrete-valued gain changes. The gain of a signal is controlled by modulating between multiple gain values for corresponding time durations, so that a resulting average gain is controlled according to the average of the multiple gain values as weighted by their corresponding time durations. The modulation frequency is above the bandwidth of the signal. Transitions between gain levels are performed by changing the relative proportion of the durations to slowly change the gain according to a transition profile, which may be linear or non-linear. The modulation employed may be pulse-width modulation, or another modulation pattern such as a delta-sigma modulation pattern.

Modulated gain audio control and zipper noise suppression techniques using modulated gain

In at least one embodiment, an electronic system includes an amplifier having an on-chip charge pump to provide a gate boost voltage to boost a gate voltage of at least one on-chip field effect transistor (FET) of an output stage of an amplifier. In at least one embodiment, the gate boost voltage boosts the gate voltage higher than the supply voltage rail to increase an overdrive voltage of the on-chip FET. In at least one embodiment, the gate boost voltage boosts the DC bias of an input signal and, thus, generation of gate boost voltage by the on-chip charge pump is signal-independent, i.e. independent of the input signal. Increasing the overdrive voltage increases the efficiency of the amplifier by decreasing the difference between the maximum swing of the output voltage and the voltage supply rails of the at least one on-chip FET relative to conventional designs.

Gate-boosted, variable voltage supply rail amplifier

A charge pump power supply for a consumer device audio power stage has an efficiency selected according to signal level. The frequency of operation of the charge pump and/or the effective size of a switching transistor bank is adjusted based upon a volume (gain) setting, or a detected signal level, so that internal power consumption of the charge pump is reduced when high output current is not required from the audio power stage and consequently from the charge pump. Operating modes of the charge pump are selected by the signal level indication and include at least a high power and a high efficiency mode selected by setting the charge pump operating frequency and/or enabling or disabling switching of one or more of multiple parallel transistors used to implement each switching element of the charge pump, thereby setting the level of gate capacitance being charged/discharged by the gate driver circuit(s).

Signal level selected efficiency in a charge pump power supply for a consumer device audio power output stage

A charge pump power supply for an audio power amplifier integrated circuit has an operating mode selected according to an indication of operating environment and/or a process position of the integrated circuit. The operating mode selects the output voltage provided by the charge pump and may also select efficiency by selecting a frequency of operation of the charge pump and/or the effective size of a switching transistor bank. The selection is made in conformity with an indication of a process position of the integrated circuit and/or an indication of an environment of the integrated circuit, such as temperature, power supply voltage and/or load impedance values, and generally also in conformity with a volume (gain) setting, or a detected signal level, so that internal power consumption of the amplifier and charge pump is reduced when a high signal level is not being reproduced at the audio power stage.

Operating environment and process position selected charge-pump operating mode in an audio power amplifier integrated circuit

A numerically-controlled phase-lock loop with input clock dependent ratio adjustment provides for narrower-bandwidth loops that lock to a wide range of frequencies and/or operation with an absent or degraded input timing reference. A timing reference characteristic detector determines an input frequency range of the input timing reference signal, the data type of the timing reference, and/or whether a timing reference signal of sufficient quality is present. A numerically controlled oscillator is controlled by a numeric ratio that is adjusted to provide the desired clock frequency output in conformity with the detected frequency range and/or data type. If the timing reference signal is absent or degraded, then the numeric ratio can be set to a fixed value or a local timing reference can be applied in order to generate the desired clock output frequency.

Numerically-controlled phase-lock loop with input timing reference-dependent ratio adjustment

A hybrid analog/digital phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A numerically-controlled analog oscillator provides a clock output and has an input for receiving a rational number. The rational number represents a ratio between the frequency of the clock output and the frequency of another stable clock provided to the circuit. A counter divides the frequency of either the clock output or the stable clock, providing feedback or feed-forward control of the analog oscillator, respectively. The circuit also includes a digital phase-frequency detector for detecting an on-going phase-frequency difference between an input timing reference and an output of the divider and a digital loop filter for filtering the output of the phase-frequency detector to provide the rational number that controls the frequency of the numerically-controlled analog oscillator.

Hybrid analog/digital phase-lock loop for low-jitter synchronization

A low-noise block (LNB) control device within a set-top box is disclosed. The LNB control device is capable of controlling modulation of an alternating waveform on a direct current (DC) voltage from a DC power supply to an LNB amplifier. The LNB control device includes a power supply control module, an LNB signaling module and a switch. In response to a power supply feedback signal received from the DC power supply, the power supply control module sends a control signal to the DC power supply. In addition, the LNB signalling module provides a switch control signal and a modulating waveform to the switch. Under the control of switch control signal, the switch selectively sends the modulating waveform to a summing circuit that is located external to the LNB control device. Within the summing circuit, the modulating waveform is added to the DC voltage from the DC power supply.

Low-noise block controller within a set-top box

An apparatus for controlling modulation of an alternating waveform on a direct current (DC) voltage signal within a low-noise block (LNB) controller is disclosed. The apparatus includes a DC power supply and a mixing/switching circuit. The DC power supply provides a steady DC voltage to a load, such as an LNB amplifier. The mixing/switching circuit adds a modulating signal to the DC voltage and selectively allows the modulated DC voltage to the load. The mixing/switching circuit includes a common control signal input for managing both of the above-mentioned two functions.

Growing community of inventors

Austin, TX, United States of America

Scott Allan Woodford