Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Other

Globalfoundries Inc.

Advanced Micro Device, Inc.

Scott Allan Bell

Christopher F Lyons

Marina V Plat

Chih Yuh Yang

Srikanteswara Dakshina-Murthy

Chih-Yuh Yang

Fei Wang

Angela Tai Hui

Harry Jay Levinson

Khanh B Nguyen

Ramkumar Subramanian

Todd P Lukanc

Philip A Fisher

Lu You

Cyrus E Tabery

Mark S Chang

Qi Xiang

Shenqing Fang

Olov B Karlsson

Douglas J Bonser

Simon S Chan

Chun Chen

Minh Van Ngo

Richard J Huang

Lei Xue

Richard C Nguyen

Bhanwar Singh

David Keating Foote

Marilyn I Wright

Phillip Lawrence Jones

Kuo-Tung Chang

Hidehiko Shiraiwa

William George En

Darin A Chan

Kouros Ghandehari

Allison Holbrook

Daniel A Steckert

Mark T Ramsbey

Jean Y Yang

Luigi Capodieci

Kashmir S Sahota

Tazrien Kamal

Uzodinma Okoroanyanwu

Alexander H Nickel

Christopher Lee Pike

Wai Lo

Michael Brennan

Chuan Lin

Gang Xue

Subash Gupta

Kenichi Ohtsuka

Bradley Marc Davis

Tom Blasingame

Calvin T Gabriel

Jeffrey Allan Shields

Dawn M Hopper

Effiong Etukudo Ibok

Robert B Ogle

Dong-Hyuk Ju

Youseok Suh

Rinji Sugino

Amol Ramesh Joshi

David E Brown

Che-Hoo Ng

Wei Long

Satoshi Torii

Hung-Eil Kim

Harpreet Kaur Sachar

Emmanuil Lingunis

Pei-Yuan Gao

Weidong Qian

John C Foster

Jusuke Ogura

David H Matsumoto

Anne E Sanderfer

Ashok M Khathuria

Khanh T Nguyen

Bill Yowjuang Liu

Lovejeet Singh

Gong Chen

Shenging Fang

David Lin

Chih-Yuk Yang

James E Hawes

Hung-Eli Kim

Amada Wilkison

A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Split-gate semiconductor device with L-shaped gate

Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device.

Ion implantation-assisted etch-back process for improving spacer shape and spacer width control

Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second mask are removed. The first mask is formed on the first polysilicon layer and the second mask is formed on the second polysilicon layer in the first region and not on in the second region.

Buried hard mask for embedded semiconductor device patterning

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.

Spacer formation with straight sidewall

An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

Integrating transistors with different poly-silicon heights on the same die

Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed.

A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.

Formation of gate sidewall structure

A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Method for forming narrow structures in a semiconductor device

A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Integrated circuit with metal and semi-conducting gate

A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Mask for forming integrated circuit

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Methods for forming a memory cell having a top oxide spacer

Integrated circuit system with metal and semi-conducting gate

Growing community of inventors

San Jose, CA, United States of America

Scott Allan Bell