International Business Machines Corporation

Other

Scott Alan Tetreault

Sebastian Theodore Ventrone

Alvar Antonio Dean

David James Hathaway

John Maxwell Cohn

Thomas M Lepsic

Amir H Farrahi

Charles N Choukalos

Jagannathan Narasimhan

David E Lackey

Susan K Lichtensteiger

Patrick Edward Perry

Carl L Ashley

The present embodiments relate to an illuminated wreath card holder comprising a wreath form, decorative material configured to create a wreath on the form, and a plurality of ornamental clamp assemblies that are attached to the wreath form and configured to releasably secure, display, and illuminate greeting cards on the wreath. Each ornamental clamp assembly comprises at least one ornamental cover, at least one clip, and at least one light that is positioned between the ornamental cover and the clip. When viewed from the front, the light is hidden behind the ornamental cover and casts a glow up onto the greeting card. The ornamental cover may be star-shaped and have a return flange at its back to which the light and clip are attached. The illuminated wreath card holder may have a power source and be packed in kit form.

Illuminated Christmas wreath card holder

An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum same-direction switching probability &#x3c6;or has an opposite-direction switching probability &#x3c6;per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability &#x3c6;. The first wire and the second wire satisfies at least one mathematical relationship involving Land Wwhere Wis defined as a spacing between the first wire and the second wire, and Lis defined as a common run length of the first wire and the second wire.

Wiring optimizations for power

An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

Remote IP simulation modeling

Both logical and physical construction of voltage islands is disclosed. A semiconductor chip design is partitioned into &ldquo;bins&rdquo;, which are areas of the design. In this way, a semiconductor chip design may be &ldquo;sliced&rdquo; into various areas and the areas may then be assigned to various voltage levels. Each bin may be thought of as a voltage island. Circuits in the design can be added to or removed from the various bins, thereby increasing or decreasing the speed and power of the circuits: the speed and power increase if a circuit is placed into a bin assigned a higher voltage, and the speed and power decrease if a circuit is placed into a bin having a lower voltage. The size and location of the bins may also be changed. By iterating these steps, the optimum power consumption may be met while still meeting speed constraints and other criteria. The present invention is applicable to any placement environment, such as an annealing placement tool, that proceeds through successive refinement of the locations of the circuits on the design and in which the placement process may be interrupted to make changes in placement of the logic.

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

In integrated circuit (IC) designs, a component of power consumed may be represented as Power&equals;&frac12; FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

Method and apparatus for reducing power consumption in VLSI circuit designs

A method for preventing illicit copying of an application specific integrated circuit (ASIC). The ASIC is defined by a net list which includes a timer circuit for disabling the ASIC. The timer circuit includes a plurality of stages which are distributed in different cores of the ASIC to inhibit detection and removal of the circuit. The timer times out after a period which is set to permit evaluation of the ASIC design. Following the time out period, further use of the ASIC design is inhibited.

Method and circuit for providing copy protection in an application-specific integrated circuit

A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

Growing community of inventors

Marlborough, MA, United States of America

Scott Alan Tetreault