Westinghouse Electric Corporation

Scott A Imhoff

Daniel C Buck

Martin G Woolfson

Dale E Dawson

James E Degenford

Soong H Lee

Giora A Bendor

James R Brinsley

Martin M Morici

Guy W Cheesman, Iii

A classifier employing general frame wavelets for improving target recognition while decreasing computational intensity is disclosed. A wavelet selection means compares a portion of a time dependent input signal from a receiver with a set of sample wavelets, each wavelet being bandpass limited, locally supported, and mean zero, and selects a prototype wavelet resembling the input portion. A resolving means expands the prototype wavelet onto a basis of wavelet functions having variations in scale and delay, and resolves the input signal onto the basis of functions. A regionpass filter identifies a region from a grid of resolved coefficients that contains features of a target from the input signal and discards coefficients outside the region. A separability filter passes select coefficients from a scale band within the identified region where separability among known targets is high. A comparator compares the selected coefficients with an exemplar of known targets to indicate a recognition of the target.

General frame wavelet classifier

A semiconductor device has material removed from the back of the substrate and a manufacturing process is provided for manufacturing these devices. In the exemplary embodiment, a GaAs FET chip is formed by a process including the step of etching the GaAs substrate from the back of the chip in a defined removal region to reduce the dielectric constant in the region of the source-to-drain path. A buffer layer of differing material provided between the active layers and the substrate prevents etching of the active layers during the removal process. To allow simplified etching patterns, the source-to-drain path may be laid out on the surface of the chip in a variety of patterns, including 'packed' patterns concentrating a large path area in a small surface area of the chip. Optionally, this buffer layer may also be etched away in a further processing step. An insulating layer of material may be added to the back side of the chip in the etched region to increase structural strength, and a pressure relief ventilation path may be provided connecting the removal region to the outside at an edge or at the surface of the chip.

Low-loss semiconductor device and backside etching method for

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Pasadena, MD, United States of America

Scott A Imhoff