Intel Corporation

Scott A Goble

Barry R Davis

David M Puffer

Bruce A Young

Michael F Cole

T Scott Cummins

A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are known as &ldquo;programmable decode modes.&rdquo; In one programmable decode mode, private address spaces are defined for allowing two or more devices interconnected to a secondary PCI bus to communicate directly using private transactions. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. Another programmable decode mode is &ldquo;intelligent&rdquo; bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus.

Method and apparatus providing an improved PCI bus system

A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.

Method and apparatus providing programmable decode modes for secondary PCI bus interfaces

A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.

Method for utilizing a single multiplex address bus between DRAM, SRAM

A PCI-to-PCI bridge is described having a processor configured for performing various routing operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are described herein as 'programmable decode modes.' In one programmable decode mode, private address spaces facilitate communication between peer PCI devices without burdening the primary PCI bus or any upstream components such as a host-to-PCI bridge, a host bus and host microprocessors. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. The transactions are routed to the primary PCI bus. Another programmable decode mode is 'intelligent' bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus. Only addresses within programmable reverse positive decode address spaces are captured by the secondary PCI interface and forwarded to the corresponding primary PCI bus. Intelligent bridging allows, among other functions, the interconnection of two peer primary PCI buses by a single PCI-to-PCI bridge. Such enables transactions between PCI devices of the peer PCI buses to be routed over the PCI-to-PCI bridge without requiring routing through a host bus.

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Chandler, AZ, United States of America

Scott A Goble