Intel Corporation

Tahoe Research, Ltd.

Scott A Gilbert

Md Altaf Hossain

John G Oldendorf

Michael Kochanowski

Shawn Lloyd

Ankireddy Nalamalpu

Ravi S Prasher

Ashay A Dani

Ajit V Sathe

Jin Zhao

An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.

Electronic chip with under-side power block

A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

Method for orienting solder balls on a BGA device

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Land side and die side cavities to reduce package z-height

Land side and die side cavities to reduce package Z-height

BGA structure using CTF balls in high stress regions

A process of making a reworkable thermal interface material is described. The reworkable thermal interface material is bonded to a die and a heat sink. The reworkable thermal interface material includes a phase-change polymer matrix material. Other materials in the reworkable thermal interface material can include heat transfer particles and low melting-point metal particles. The phase-change polymer matrix material includes a melting temperature below a selected temperature and the heat transfer particles have a melting temperature substantially above the selected temperature. The heat transfer particles act as a spacer limit, which holds the thermal interface material to a given bond-line thickness during use.

Reworkable thermal interface material

A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.

Making electrical connections between a circuit board and an integrated circuit

A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.

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Chandler, AZ, United States of America

Scott A Gilbert