Hewlett-packard Company

Scott A Dresser

Richard B Goud

Scott A Markinson

Raymond A Ward

An apparatus is provided for determining a configuration of memory modules. Each of the memory modules produces presence detect bits. In a first feature, the apparatus includes an external register for receiving the presence detect bits from the memory modules in parallel and a memory controller integrated circuit. The memory controller integrated circuit includes an internal register for storing the presence detect bits and logic circuitry for determining a memory configuration. The presence detect bits are serially transferred from the external register to the internal register. In a second feature, the logic circuitry for determining a memory configuration includes comparator circuitry for comparing the presence detect bits of each pair of memory modules and generating a match signal or a mismatch signal. When a match signal occurs, the presence detect bits of the memory module pair are loaded into a memory configuration register. When a mismatch signal occurs, a mismatch code is loaded into the memory configuration register.

Apparatus for determining a computer memory configuration of memory

A memory controller for controlling access to a memory includes a circuit for generating memory signals, including address and control signals, for accessing a memory in response to a physical address, and a circuit for programming the timing of the memory signals in response to predetermined timing control information which defines the timing requirements of the memory. The circuit for programming the timing of the memory preferably includes a register for storing timing control bits and selectors responsive to the timing control bits for selecting timing control parameters from a group of predetermined timing control parameters. The circuit for programming the timing preferably further includes a circuit responsive to each timing control parameter and to a selected memory signal for generating a timing control signal. The timing control signal controls the timing of one of the memory signals. The timing parameters can specify the duration of a memory signal or the time delay between a predefined event in one memory signal and a predefined event in another memory signal. The programmable feature permits the memory controller to be utilized with memories having different timing requirements.

Memory controller with programmable timing

A memory controller for controlling access to a memory includes a mapper for mapping a physical address to a row address and a column address that are suitable for addressing first and second memory devices having the same memory capacity but different addressing formats, a multiplexer for multiplexing the row address and the column address onto a set of address lines for addressing the memory and a circuit for generating control signals for controlling access to the memory. In a preferred embodiment, the first memory devices are 16 Mb DRAMs which require asymmetric addressing, and the second memory devices are 16 Mb DRAMs which require symmetric addressing. The memory controller of the invention generates a row address and a column address for addressing both types of memory devices without having knowledge of the types of memory devices that are present in the memory.

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Hudson, MA, United States of America

Scott A Dresser