Motorola Corporation

Spectrum Cvd, Inc.

Schyi-Yi Wu

J B Price

Curtis D Moyer

Israel A Lesk

Jenn-Hwa Huang

Hang M Liaw

Steven A Voight

Yu C Chow

John Mendonca

Bruce A Bernhardt

Jonathan K Abrokwah

Syd R Wilson

Faivel S Pintchovski

Jaeshin Cho

Gregory L Hansell

Charles T Keller

Arthur T Lowe

A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Self-aligned FET having etched ohmic contacts

Compound semiconductor devices (10, 11) having isolation regions (37) under gate pads (24, 27) and a method of forming the compound semiconductor devices (10, 11). A surface protection layer (33) is formed on a compound semiconductor substrate (31). The surface protection layer (33) is patterned to form a plurality of islands (34). A field oxide (28) is formed on the regions of the compound semiconductor substrate (31) adjacent the plurality of islands (34) and surrounds active device regions (12, 13). Isolation regions (37) are formed around active device regions (12, 13). Control electrodes (21, 22) are formed in contact with the active device regions (12, 13) and extend over the field oxide (28). Source/drain regions (16, 17) are formed adjacent the control electrodes (21, 22). Source/drain electrodes (18, 19) are formed in contact with the source/drain regions (16, 17), thereby forming field effect transistors.

Method of forming isolation region in a compound semiconductor substrate

An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

Ohmic contact for III-V semiconductor materials

Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.

Self-aligned complementary HFETS

Method of forming an ohmic contact to III-V semiconductor materials

A plasma containing both beryllium ions and beryllium fluoride ions is achieved. Beryllium crystals are used as a cathode in an ionization chamber containing boron trifluoride gas. The boron trifluoride gas and the beryllium are ionized to produce both beryllium fluoride ions (BeF.sup.+) and beryllium ions (Be.sup.+). Beryllium fluoride ions are emitted to impact a semiconductor target and where they divide thereby implanting beryllium and fluorine.

Producing a plasma containing beryllium and beryllium fluoride

A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.

Complementary heterojunction field effect transistor with an anisotype N+ g

A process is disclosed for depositing tungsten non-selectively on conductors and dielectrics without the use of an adhesive interlayer. The process comprises an argon pre-treatment followed by low power plasma deposition to nucleate the tungsten. A thick, adherent layer of tungsten is then deposited.

Blanket tungsten deposition for dielectric

A process for forming a bonding layer comprising amorphous silicon, titanium, chromium, or tungsten, between the silicide and the N+ polysilicon layer is disclosed. The bonding layer is preferably less than 50 nm. thick. After the bonding layer is deposited, a silicide layer is deposited and the wafer is then sintered at 900.degree.-1000.degree. C. for ten minutes or less.

Silicide to silicon bonding process

Chemical vapor deposition on a semiconductor wafer is obtained in a plasma reactor having a plurality of lamps for radiantly heating the wafer. Calibrated temperature sensing means remote from the wafer is used to control the heating of the wafer. Gases are supplied by way of a plurality of tubes extending radially inwardly from the sides of the chamber. A baffle is provided to form an antechamber which aids in the uniformity of the deposition. The plasma is ignited for less than the whole deposition cycle for deposition of tungsten disilicide.

Plasma enhanced CVD

Gate current leakage is reduced in a submicron FET device by the deposition of an oxide layer over the gate prior to the rapid heating of the device. This is done to prevent the dopant that was implanted into the gate from collecting on the sidewalls of the gate and the oxide layer between gate and substrate. Otherwise the diffused dopant becomes the path of least resistance, thus creating current leakage from the gate to source or gate to drain.

Fabricating a semiconductor device with reduced gate leakage

Implanting, with low energy (e.g. 75 Kev and below), a dose of boron difluoride (BF.sub.2) into an area on a silicon substrate which is post-damaged or pre-damaged by a silicon implant so that annealing, or activation, can be accomplished at temperatures in the range of 550.degree. C. to 900.degree. C.

Growing community of inventors

Mesa, AZ, United States of America

Schyi-Yi Wu