Samsung Electronics Co., Ltd.

Sayoon Kang

Jaehyun Lim

Donghan Kim

Jangwoo Lee

Chungsun Lee

Yonghoon Kim

Jaehoon Choi

Yonghwan Kwon

Kyoungsei Choi

Jongkook Kim

Taewook Kim

Jooyoung Choi

Yuntae Lee

Hwanggil Shim

Hwasub Oh

A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

Semiconductor package

Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.

Semiconductor package including multiple semiconductor chips

Package-on-package (POP) devices and methods of manufacturing the POP devices are provided. In the POP devices, a thermal interface material layer disposed between lower and upper semiconductor packages may contact about 70% or greater of an area of a top surface of a lower semiconductor chip. According to methods, the upper semiconductor package may be mounted on the lower semiconductor chip using a weight.

Package-on-package devices and methods of manufacturing the same

A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive.

Bump structure for a semiconductor device and method of manufacture

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Suwon-si, South Korea

Sayoon Kang