Sunrise Memory Corporation

University of California

Purdue Research Foundation

Sonera Magnetics, Inc.

Sonera, Inc.

Sayeef Salahuddin

Eli Harari

Robert D Norman

Khandker N Quader

Christopher John Petti

Scott Brad Herner

Siu Lung Chan

Frank Sai-Keung Lee

Mehrdad Mofidi

Tianhong Yan

Supriyo Datta

Youn Cheul Kim

Richard S Chernicoff

George Samachisa

Wu-Yi Henry Chien

Dominic Labanowski

Shehrin Sayed

Yang Yang

Jeffrey Bokor

Behtash Behin-Aein

Kerem Yunus Camsari

Jon Gorchon

Srikant Srinivasan

Richard Brian Wilson

Angik Sarkar

Robert D Normal

Charles Henri Alexandre Lambert

Dominic E Labanowski

A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

High capacity memory circuit with low effective latency

An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

Device with embedded high-bandwidth, high-capacity memory using wafer bonding

A system for an acoustically driven ferromagnetic resonance (ADFMR) based sensor. The system may include a power source, that provides an electrical signal to power the system, at least one circuit comprising a set of ADFMR circuits, sensitive to external electromagnetic fields, a power splitter, a power combiner and a detector circuit. The system functions to detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuits due to the EM fields.

System for an acoustically driven ferromagnetic resonance sensor device

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Cool electron erasing in thin-film storage transistors

Memory device including modular memory units and modular circuit units for concurrent memory operations

An acoustically driven ferromagnetic resonance (ADFMR) device includes a piezoelectric element, a pair of transducers arranged to activate the piezoelectric element to generate an acoustic wave, a magnetostrictive element arranged to receive the acoustic wave, and a readout circuit to detect one of either a change in the magnetostrictive element or a change in the acoustic wave.

Magnetic field sensor using acoustically driven ferromagnetic resonance

A system and method for design and operation an acoustically driven ferromagnetic resonance (ADFMR) based sensor for measuring electromagnetic fields that includes: a power source providing an electrical signal to an ADFMR circuit, sensitive to electromagnetic fields, wherein the ADFMR circuit comprises an ADFMR device. The system detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuit due to the EM fields. The system and method may function to facilitate the design and operation of a chip-scale ADFMR device usable to measure EM fields.

System and method for an acoustically driven ferromagnetic resonance sensor device

The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M&#x3a9;, and is eligible to exhibit a '1' state and a '0' state and exhibit a resistance change between the &#x2018;1&#x2019; state and the &#x2018;0&#x2019; state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the &#x2018;1&#x2019; state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the &#x2018;0&#x2019; state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

Voltage-controlled gain-cell magnetic memory

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between &#x2212;1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

Implementing logic function and generating analog signals using NOR memory strings

Growing community of inventors

Walnut Creek, CA, United States of America

Sayeef Salahuddin