Panasonic Intellectual Property Management Co., Ltd.

Sayaka Matsumoto

Ken Yanai

Ryosuke Usui

Yuji Yamagishi

Naoki Mutou

Masashi Takamura

Masaya Hattori

Tomomitsu Muraishi

Tomokazu Yamaguchi

It is aimed to provide a laminated varistor capable of reducing stray capacitance to occur between an internal electrode and an external electrode, and also capable of reducing a variation in the stray capacitance due to a variation in the external electrode. A laminated varistor of the present disclosure has external electrodes on first end surface, second end surface, and first side surface of sintered body. No external electrode is provided on second side surface opposite to first side surface. Varistor regions in which internal electrodes overlap each other in a laminating direction are provided at positions closer to second side surface than to first side surface.

Chip resistor for reducing stray capacitance

A sintered body that includes ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.

Multilayer electronic component production method

Growing community of inventors

Hokkaido, Japan

Sayaka Matsumoto