Texas Instruments Corporation

Saya Goud Langadi

Alexander Tessarolo

Prasanth Viswanathan Pillai

David Peter Foley

Padmini Sampath

Srinivasa Chakravarthy Bs

Venkatesh Natarajan

Shailesh Ganapat Ghotgalkar

Rajeev Suvarna

Chirag Sureshchandra Gupta

Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Methods, apparatus, and articles of manufacture to determine memory access integrity based on feedback from memory

A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

Error detection circuit

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

Instruction packing scheme for VLIW CPU architecture

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Lockstep comparators and related methods

A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.

High resolution capture

A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus ('BGMTA')) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a 'golden CRC.' If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

Background memory test apparatus and methods

A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

Multi master arbitration scheme in a system on chip

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

System and method for improving ECC enabled memory timing

A memory system includes a memory and a memory controller coupled to the memory. The memory controller includes a data buffer configured to store a full data word as a result of a partial write operation, wherein for a subsequent partial write operation, data is read from the data buffer.

Partial-writes to ECC (error check code) enabled memories

A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output.

Missing clock circuit switching clock from second to first clock

Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secondary clock counter. A clock gated register circuit is clocked by the secondary clock pulse, and is configured to store a plurality of values of the GRAY code sequence, and update the plurality of values of the GRAY code sequence on each saturation of the secondary clock counter. An error detection circuit is configured to output a detection signal for detecting the malfunction of primary clock based on a comparison of the updated plurality of values of the GRAY code sequence with at least one predetermined threshold associated with the malfunction of primary clock.

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Saya Goud Langadi