California Institute of Technology

The United States of America As Represented by the Administrator

Savio N Chau

Robert D Rasmussen

Huy H Luong

Leonard Day

Leon Alkalai

Ryan Fukuhara

Ann T Tai

David A Rennels

Systems and techniques for implementing fault-tolerant communication channels and features in communication systems. Selected commercial-off-the-shelf devices can be integrated in such systems to reduce the cost.

Fault-tolerant communication channel structures

In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, cyclic redundancy check (CRC), and byte count check operations. The I2C bus controller may include a control unit connected to an I2C core module having a base address. The I2C bus controller may also include a second I2C core module having a base address plus one (BP ). The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or, in the master mode, from itself through the BP I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus. The control unit may format CRC values and byte count values into messages, and include a byte counter to compare actual bytes received to the expected byte count indicated by a received byte count value.

I2C bus protocol controller with fault tolerance

A fault-tolerant random access memory for use in fault-tolerant computers. It comprises a plurality of memory chips each comprising a plurality of on-line testable and correctable memory cells disposed in rows and columns for holding individually addressable binary bits and provision for error detection incorporated into each memory cell for outputting an error signal whenever a transient error occurs therein. Each of the memory cells comprises a pair memory sub-cells for simultaneously receiving and holding a common binary data bit written to the memory cell and the error detection provision comprises comparator logic for continuously sensing and comparing the contents of the memory sub-cells to one another and for outputting the error signal whenever the contents do not match. In accordance with one feature of the invention, the memory systematically searches for an error in response to an error signal and corrects the error found by the search.

Self-checking on-line testable static ram

Growing community of inventors

Hacienda Heights, CA, United States of America

Savio N Chau