Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Other

Saverio Pezzini

Roberto Ganzelmi

Paolo Marceca

Alberto Ferrari

Maurizio Peri

Alessandro Pepi

Paolo Brasca

An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Method for controlling interrupts and auxiliary control circuit

A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.

Bus architecture with primary bus and secondary or slave bus wherein transfer via DMA is in single transfer phase engagement of primary bus

A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller

A serial interface for communicating with peripherals may include a circuit for generating pointers to addresses in sections of a memory, and a circuit for serially transferring data from or to at least one peripheral connected to the interface that is coupled to the memory based upon requisite configuration commands. The interface may further include a control register coupled to the memory and to the serial transfer circuit for controlling data to be transmitted or received. The interface does not require that an external controller provide configuration commands each time data is transmitted or received because the memory sections for storing data may be divided in distinct memory spaces. That is, each memory space may store data for a respective peripheral connected to the interface. Moreover, another memory section may be used to store all of the configuration commands of the interface required for communicating with the peripherals.

Serial peripheral interface and related methods

An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Integrated analog-to-digital converter with detection of external faults

A control device for a vehicle engine includes a memory unit for storing engine configuration parameters, a processing unit for sending control signals to the engine in accordance with the configuration parameters, and an input/output unit connectible to an external computer to modify the configuration parameters. The control device includes a first portion and a second portion of the memory unit, with each portion being alternately used in an active state for storing a current version of the configuration parameters or in an inactive state for the writing of a new version of the configuration parameters. The processing unit accesses the portion which is in the active state for reading, and the input/output unit accesses the portion which is in the inactive state for writing. An interconnection unit selectively switches one of the portions to the active state and the other of the portions to the inactive state.

Control device for a vehicle engine

A capacitive array particularly for converters, comprising a plurality of unitary capacitors, the number of the unitary capacitors being equal to 2.sup.n, where n is the number of bits of the binary code required in output, the unitary capacitors being mutually connectable so as to obtain capacitors in which the capacitance ratio between one capacitor and the adjacent parallel-connected capacitor is equal to a factor of two. The invention is that the factor-of-two capacitance ratio of adjacent capacitors is achieved by mutually diagonally connecting in parallel the unitary-capacitance capacitors of the capacitive array in a preset number according to the capacitance value to be obtained.

Capacitive array having a correct capacitive ratio among the component

A method whereby the N elements of a memory are read sequentially, and the data items contained therein are compared with reference data items. Simultaneously with the reading of each element of the memory, its address is written in a number of redundancy check registers, each connected to a respective redundancy element. In the event the element of the memory differs from the reference data item, the first of the redundancy check registers is blocked to prevent it from being overwritten and the address of a faulty element of the memory is permanently stored. Upon the entire memory being read, the addresses of any faulty elements in the memory are thus already stored in the redundancy check registers.

Method for detecting faulty elements of a redundancy semiconductor memory

A protection circuit (1) comprising a first and second supply line at a first and second supply voltage respectively; a reference voltage source; a comparator connected to the first supply line and the source; and a switch controlled by the comparator via a control terminal and located between the second supply line and the output of the circuit. To reduce static consumption of the comparator under normal operating conditions, the circuit comprises enabling control elements connected to the two supply lines and to the comparator for disabling the comparator and turning on the switch when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.

Protection circuit for devices comprising nonvolatile memories

A method is provided for directly reading the current of cells of a memory forming part of a microcontroller by performing a write operation of the cells and using the existing cell programming logic. For this purpose, the programming voltage supply line is supplied with a low voltage (e.g., 1 V); the word line of the cell for reading is enabled; and a write instruction of a data item having a predetermined logic level (e.g., zero) is performed at the bit corresponding to the cell for reading. By providing an additional pass transistor connected to each reference bit line (RBL) and an additional reference cell enabling line (REF-EN), the reference cells may also be read directly.

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Vimercate, Italy

Saverio Pezzini