Cavium, Inc.

Fungible, Inc.

Microsoft Technology Licensing, LLC

Marvell Asia Pte., Ltd.

Saurin Patel

Keqin Han

Nimalan Siva

Tsahi Daniel

Deepak Goel

Srihari Raju Vegesna

John David Huber

Pradeep S Sindhu

Gerald Schmidt

Ayaskant Pani

Chirinjeev Singh

Narendra Jayawant Gathoo

Rohit Sunkam Ramanujam

Vamsi Panchagnula

Mohan Balan

Jean-Marc Frailong

Weihuang Wang

Hariharan Lakshminarayanan Thantry

Vikas Minglani

Stimit Kishor Oak

Sureshkumar Nedunchezhian

Polasanapalli Sri Devi

Sri Devi Polasanapalli

Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.

Resilient network communication using selective multipath packet flow spraying

An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.

Method and apparatus for using multiple linked memory lists

Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.

Flexible processing of network packets

An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams. A processor coupled to the ingress port, to identify source data of the multicast data packets of the data streams to match the multicast data packets with available egress ports. The processor to determine, using the identified source and status data which of the multicast data packets matches the available egress ports. The processor to select a first data path coupled to the egress port to transmit the matched multicast data packets to available egress ports where the selected first data path is configured to enable the direct transmission of the matched multicast data packets to available egress ports.

Method and apparatus for bypass routing of multicast data packets and avoiding replication to reduce overall switch latency

A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Testbench builder, system, device and method

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.

Apparatus and method for optimized n-write/1-read port memory design

Testbench builder, system, device and method including latency detection

Testbench builder, system, device and method having agent loopback functionality

Testbench builder, system, device and method with phase synchronization

Embodiments of the apparatus for modifying packet headers relate to pointer structure for splitting a packet into individual layers and for intelligently stitching them back together. The pointer structure includes N+1 layer pointers to N+1 protocol headers. The pointer structure also includes a total size of all headers. A rewrite engine uses the layer pointers to extract the first N corresponding protocol layers within the packet for modification. The rewrite engine uses the layer pointers to form an end point, which together with the total size of all headers is associated with a body of the headers. The body of the headers is a portion of headers that are not modified by the rewrite engine. After all the modifications are performed and modified headers are compressed, the modified layer pointers are used to stitch the modified headers back together with the body of the headers.

Method of splitting a packet into individual layers for modification and intelligently stitching layers back together after modification and an apparatus thereof

Embodiments of the apparatus for modifying packet headers relate to programmable modifications of packets by applying commands to generalized protocol headers. Each protocol header of incoming packets is represented in a generic format specific to that protocol to enable modifications to packet headers. Missing fields from a protocol header are detected, and the protocol header is expanded to a maximum size such that the protocol header contains all possible fields of that protocol, including the missing fields. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. Modification uses a set of commands that is applied to expanded protocol headers. All of the commands are thus generic as these commands are independent of incoming headers (e.g., size and protocol).

Method of using generic modification instructions to enable flexible modifications of packets and an apparatus thereof

Testbench builder, system, device and method including a generic monitor and transporter

Growing community of inventors

San Jose, CA, United States of America

Saurin Patel