Synopsys, Inc.

Saurav Nanda

Ganapathy Parthasarathy

Parivesh Choudhary

Pawan Patil

Arun Venkatachar

Bhuvnesh Kumar

Sridhar Rajakumar

Certain aspects of the present disclosure are directed towards a method for circuit testing. The method generally includes: determining a probability distribution indicating prior failure probabilities associated with a circuit design; determining a first likelihood associated with occurrence of at least one failure for the circuit design; determining a quantity of test instances to be performed using simulation to detect the at least one failure based on the probability distribution and the first likelihood; and outputting the quantity of test instances.

Constrained random simulation using machine learning and Bayesian estimation

Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.

Automated translation of design specifications of electronic circuits

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San Jose, CA, United States of America

Saurav Nanda