Texas Instruments Corporation

Massachusetts Institute of Technology

Massachusetts Eye and Ear Infirmary

Saurav Bandyopadhyay

Robert Allan Neidorff

Jeffrey Anthony Morroni

Thomas Matthew LaBella

Kevin Scoones

Orlando Lazaro

Reza Sharifi

Alvaro Aguilar

Yogesh Kumar Ramadass

Salvatore Giombanco

Michael G Amaro

Rosario Davide Stracquadaini

Todd Allen Toporski

Yongbin Chu

Huy Le Nhat Nguyen

Anantha P Chandrakasan

Patrick Mercier

Konstantina Stankovic

Ramanathan Ramani

Michael Thomas DiRenzo

Song Guo

Taisuke Kazama

Monodeep Kar

Tianyu Chang

Andrew Lysaght

Bradley Zarek

Jianbo Gou

Anthony Fagnani

Nilanjan Pal

In some examples, an apparatus includes a constant amplitude ramp generator having a differential output and first and second generator inputs, in which the first generator input is coupled to a power terminal. The apparatus also includes an input voltage feed-forward circuit having a feed-forward input and a feed-forward output, in which the feed-forward input is coupled to an input voltage terminal, and the feed-forward output is coupled to the second generator input.

Input voltage feedforward in constant amplitude ramp

A circuit includes a comparator having first and second comparator inputs and a comparator output. A discharge switch is coupled between the first comparator input and a ground terminal. A capacitor has first and second capacitor terminals, in which the first capacitor terminal is coupled to the first comparator input. A delay correction circuit includes a sample-hold circuit coupled to the first capacitor terminal and the second capacitor terminal. An amplifier has a first amplifier input coupled to a hold output of the sample-hold circuit and a second amplifier input coupled to the second comparator input. A variable resistor is coupled between the second capacitor terminal and the ground terminal, and has a control input coupled to the amplifier output.

Delay correction for on-time generator circuitry

An active electromagnetic interference (EMI) filter includes a first amplifier and a second amplifier. The first amplifier is configured to sense noise signals on a power conductor. The second amplifier is coupled to the first amplifier and is configured to drive a cancellation signal onto the power conductor. The cancellation signal is to reduce the amplitude of the noise signals sensed by the first amplifier. An output impedance of the second amplifier is lower than an output impedance of the first amplifier.

Cascaded active electro-magnetic interference filter

A current sense circuit includes a sense amplifier, a current mirror circuit, a resistor, a low-pass filter, and a capacitor. The sense amplifier is adapted to be coupled to a switching transistor of a DC-DC converter. The current mirror circuit is coupled to the sense amplifier, and is configured to generate a sense current proportional to a current flowing through the switching transistor. The resistor is coupled to the current mirror circuit, and is configured to generate a sense voltage based on the sense current. The low-pass filter is coupled to the resistor, and is configured to average the sense voltage over an averaging interval. The capacitor is coupled to the resistor, and is configured to store the sense voltage in a blanking interval that precedes the averaging interval, and provide a compensation current in the averaging interval.

Current sensing with capacitive compensation

Embodiments include systems, methods, and apparatuses for controlling off-time during a burst mode in an LLC converter. In one embodiment, a circuit comprises an LLC converter having a primary side and a burst mode controller, the burst mode controller configured to monitor, on the primary side of the LLC converter, electrical current, and in response to a determination that the electrical current is below a first threshold, increase an off-time for switches in the LLC converter and in response to a determination that the electrical current is above a second threshold that is higher than the first threshold, decrease the off-time for the switches in the LLC converter.

Primary side burst mode controller for LLC converter

Methods and apparatus to provide an adaptive gate driver for switching devices are disclosed. An example apparatus includes an electrical switch to drive an electrical system; a condition characterizer to select a drive strength based on a first system parameter corresponding to the electrical system, the first system parameter including at least one of an input voltage corresponding to the electrical switch, an output current corresponding to the electrical switch, or a process variation of the electrical switch; and a driver to generate an output having a current corresponding to the selected drive strength.

Methods and apparatus to provide an adaptive gate driver for switching devices

In described examples of a ramp circuit, a first terminal of a capacitor is coupled to a ramp terminal and a second capacitor terminal is coupled to a return terminal. A charge source has an input terminal coupled to a supply terminal and a charge output terminal. A resistor has a first terminal coupled to the return terminal. A first switch is coupled between the ramp terminal and a second terminal of the resistor. A second switch is coupled between the charge output terminal and the ramp terminal.

Constant amplitude ramp generator

A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.

Switch-mode power supply with load current based throttling

In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.

Semiconductor process variation detector

In a described example, an apparatus includes a first switch coupled between a terminal for receiving an input voltage and a top plate node, and having a first control terminal; a second switch coupled between the top plate node and a switching node, and having a second control terminal; a third switch coupled between the switching node and a bottom plate node and having a third control terminal; a fourth switch coupled between the bottom plate node and a ground terminal, and having a fourth control terminal; a flying capacitor coupled between the top plate node and the bottom plate node; a fifth switch coupled between the top plate node and an auxiliary node; a sixth switch coupled between the auxiliary node and the bottom plate node; and an auxiliary capacitor coupled between the auxiliary control terminal and a ground terminal.

Three-level converter using an auxiliary switched capacitor circuit

A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.

Adaptive synchronous rectification in a voltage converter

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.

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Dallas, TX, United States of America

Saurav Bandyopadhyay