Intel Corporation

Saurabh Tangri

Varghese George

Prasoonkumar Surti

Selvakumar Panneer

Abhishek R Appu

Joydeep Ray

Altug Koker

Elmoustapha Ould-Ahmed-Vall

Vasanth Ranganathan

Scott R Janus

Aravindh V Anantaraman

Mike MacPherson

Lakshminarayanan Striramassarma

Subramaniam M Maiyuran

Ankur N Shah

Carl S Marshall

Ben J Ashbaugh

Niranjan L Cooray

Valentin Andrei

Nilesh K Jain

Jill MacDonald Boyce

Glen J Anderson

Adam T Lake

Nicolas C Galoppo Von Borries

David M Puffer

Deepak Shashidhar Vembar

Karthik Veeramani

Soethiha Soe

Kamal Sinha

Ravishankar Iyer

Eric C Samson

Pattabhiraman K

Josh B Mastronarde

Brent E Insko

Rajeev K Nalawadi

Arthur Hunter, Jr

Nilay Mistry

Jayakrishna P S

Satyam Srivastava

Nicolas Galoppo Von Borries

An apparatus to facilitate video motion smoothing is disclosed. The apparatus comprises one or more processors including a graphics processor, the one or more processors including circuitry configured to receive a video stream, decode the video stream to generate a motion vector map and a plurality of video image frames, analyze the motion vector map to detect a plurality of candidate frames, wherein the plurality of candidate frames comprise a period of discontinuous motion in the plurality of video image frames and the plurality of candidate frames are determined based on a classification generated via a convolutional neural network (CNN), generate, via a generative adversarial network (GAN), one or more synthetic frames based on the plurality of candidate frames, insert the one or more synthetic frames between the plurality of candidate frames to generate up-sampled video frames and transmit the up-sampled video frames for display.

Video smoothing mechanism

Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.

Graphics processor data access and sharing

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

Multi-tile architecture for graphics operations

Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

Assistance for hardware prefetch in cache access

Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.

Neural network processing for multi-object 3D modeling

Growing community of inventors

Rocklin, CA, United States of America

Saurabh Tangri